Year : 2021
Hardware Realization of Low power and Area Efficient Vedic MAC in DSP Filters
Cite this Research Publication : D. S. Manikanta, K. S. S. Ramakrishna, M. Giridhar, N. Avinash, T. Srujan and R. S. R, "Hardware Realization of Low power and Area Efficient Vedic MAC in DSP Filters," 2021 5th International Conference on Trends in Electronics and Informatics (ICOEI), 2021, pp. 46-50, doi: 10.1109/ICOEI51242.2021.9453041.
Publisher : 2021 5th International Conference on Trends in Electronics and Informatics (ICOEI)
Year : 2021
A Low Power Signed Redundant Binary Vedic Multiplier
Cite this Research Publication : C. Mahitha, S. C. S. Ayyar, S. D. B, A. Othayoth and R. S R, "A Low Power Signed Redundant Binary Vedic Multiplier," 2021 5th International Conference on Trends in Electronics and Informatics (ICOEI), 2021, pp. 76-81, doi: 10.1109/ICOEI51242.2021.9453032.
Publisher : 2021 5th International Conference on Trends in Electronics and Informatics (ICOEI)
Year : 2021
Design of Combinational Arithmetic Circuits using Quantum Dot Cellular Automata
Cite this Research Publication : S. Prasanna A, B. Madhava Reddy and R. S R, "Design of Combinational Arithmetic Circuits using Quantum Dot Cellular Automata," 2021 5th International Conference on Trends in Electronics and Informatics (ICOEI), 2021, pp. 117-122, doi: 10.1109/ICOEI51242.2021.9453069.
Publisher : 2021 5th International Conference on Trends in Electronics and Informatics (ICOEI)
Year : 2021
Hardware Trojan Detection using Ring Oscillator
Cite this Research Publication : D. S, R. S. R and N. D. M, "Hardware Trojan Detection using Ring Oscillator," 2021 6th International Conference on Communication and Electronics Systems (ICCES), 2021, pp. 362-368, doi: 10.1109/ICCES51350.2021.9488935.
Publisher : 6th International Conference on Communication and Electronics Systems (ICCES)
Year : 2020
A Low Delay Architecture for Logarithmic Multiplication
Cite this Research Publication :
P. Kumar Kssrb, N., S. Shantan, S., P., V., B. R., and Ramesh S. R., “A Low Delay Architecture for Logarithmic Multiplication”, 2020 4th International Conference on Trends in Electronics and Informatics (ICOEI)(48184). 2020.
Publisher : International Conference on Trends in Electronics and Informatics (ICOEI)(48184)
Year : 2019
Low Power Cubic Computation Unit Using Vedic Sutras
Cite this Research Publication :
P. Aatmica, Ranjith, V., Nimalsurya, I., and Ramesh S. R., “Low Power Cubic Computation Unit Using Vedic Sutras”, IOP Conference Series: Materials Science and Engineering, vol. 561, p. 012114, 2019.
Publisher : IOP Publishing
Year : 2018
Statistical Viability Analysis and Optimization through Gate Sizing
Cite this Research Publication :
K. Sreenath and Ramesh S. R., “Statistical Viability Analysis and Optimization through Gate Sizing”, Lecture Notes in Electrical Engineering, vol. 475, pp. 149-155, 2018.
Publisher : Springer, Singapore
Year : 2017
Design of an Enhanced Array Based Approximate Arithmetic Computing Model for Multipliers and Squarers
Cite this Research Publication :
H. Haritha and Ramesh S. R., “Design of an Enhanced Array Based Approximate Arithmetic Computing Model for Multipliers and Squarers”, 2017 14th IEEE India Council International Conference (INDICON). 2017.
Publisher : 2017 14th IEEE India Council International Conference (INDICON)
Year : 2016
Improved Statistical Static Timing Analysis Using Refactored Timing Graphs
Cite this Research Publication :
Ramesh S. R. and Jayaparvathy, R., “Improved Statistical Static Timing Analysis Using Refactored Timing Graphs”, Journal of Computational and Theoretical Nanoscience, vol. 13, pp. 8879-8884, 2016.
Publisher : Journal of Computational and Theoretical Nanoscience
Year : 2015
Probabilistic activity estimator and timing analysis for LUT based circuits
Cite this Research Publication :
Ramesh S. R. and Jayaparvathy, R., “Probabilistic activity estimator and timing analysis for LUT based circuits”, International Journal of Applied Engineering Research, vol. 10, pp. 33238-33242, 2015.
Publisher : Research India Publications
Year : 2015
Early Stage FPGA Architecture Development by Exploiting Dependence on Logic density
Cite this Research Publication :
P. L. Paleri and Ramesh S. R., “Early Stage FPGA Architecture Development by Exploiting Dependence on Logic density”, International Journal Of Applied Engineering Research, vol. 10, no. 11, pp. 28889-28902, 2015.
Publisher : International Journal Of Applied Engineering Research
Year : 2014
A Survey of SSTA Techniques with Focus on Accuracy and Speed
Cite this Research Publication : Bhaghath P J,Ramesh S R "A Survey of SSTA Techniques with Focus on Accuracy and Speed" , published in the International Journal of Computer Applications (0975 – 8887), Volume 89 – No.7, March 2014.
Publisher : International Journal of Computer Applications
Year : 2012
Toggle Rate Estimation Technique for 4-Input LUT based FPGA Circuits
Cite this Research Publication : Anju.P.J, Ramesh.S.R “Toggle Rate Estimation Technique for 4 input LUT based FPGA circuits” in International Journal of Engineering Research and Applications vol.2,no.3 pp 198-203,May-June2012
Publisher : International Journal of Engineering Research and Applications
Year : 2012
An Approach towards Logic Synthesis by Functional Decomposition
Cite this Research Publication : Athira .P.V, Ramesh.S.R “ An Approach towards Logic Synthesis by Functional Decomposition” in International Journal of Engineering Research and Applications vol.2,no.3 pp 324-330,May-June2012
Publisher : International Journal of Engineering Research and Applications