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Dr. Ramesh S. R.

Assistant Professor (S.G), Electronics and Communication Engineering, School of Engineering, Coimbatore

Qualification: M.E, Ph.D
sr_ramesh@cb.amrita.edu
Ph: +91- 9894391731, +91 422 2685000 Ext. 5731
Ramesh S. R's Google Scholar Profile Added
Research Interest: Embedded Sensor Networks, FPGA Logic Architectures, Static Timing Analysis, VLSI CAD, VLSI Design

Bio

Dr. Ramesh S. R. currently serves as an Assistant Professor (Senior Grade) in the Department of ECE, Ettimadai Campus. He joined Amrita in July 2007. He completed his Ph.D in Static Timing Analysis from Anna University, Chennai in 2020 and Master of Engineering in VLSI Design from Arulmigu Kalasalingam College of Engineering (Anna University, Chennai ) in 2007. He did his Bachelor of Engineering in ECE from Cape Institute of Technology (Anna University, Chennai) in 2005. His areas of interest include Static Timing analysis, Hardware Trojan Detection, VLSI CAD, FPGA Logic Architectures, Low power VLSI, IOT and Embedded Sensor Networks. He is an Associate Member in IETE. He is a reviewer for many reputed International Journals. He is currently guiding research scholars and serves as a Doctoral Committee member for various students.

Education

  • Ph. D. in VLSI
    Anna University, Chennai
  • 2007: M. E. in VLSI
    Anna University, Chennai/ Arulmigu Kalasalingam College of Engineering

Professional Experience

Year Affiliation
July 2011 to till date Assistant Professor (Sr. Gr), Amrita Vishwa Vidyapeetham
Domain : Teaching, Research
July 2009 to June 2011 Assistant Professor, Amrita Vishwa Vidyapeetham
Domain : Teaching, Research
July 2007 to June 2009 Lecturer, Amrita Vishwa Vidyapeetham
Domain : Teaching

Academic Responsibilities

SNo Position Class / Batch Responsibility
1. Batch Coordinator 2015-19 Coordinating class Advisers for smooth conduct of academics
2. Class Adviser 2015 – 19 EIE Monitoring Students and counseling
3. Mentor Open Lab 2017-18 Third Year ECE and EIE Facilitates hardware prototyping and arrangement of resources
4. Project Coordinator 2018-19 Final Year ECE and EIE Coordinating class Advisers for conduct of project reviews

Undergraduate Courses Handled

  1. CMOS Integrated Circuits
  2. Electronics Engineering
  3. Electronic Circuits
  4. VLSI Design
  5. VLSI Technology
  6. Linear Integrated Circuits

Post-Graduate / PhD Courses Handled

  1. Solid State Devices (VLSI Design)
  2. CAD for VLSI (VLSI Design)
  3. Micro Electromechanical Systems (VLSI Design)
  4. Static Timing Analysis (VLSI Design)
  5. Analysis and Design of Mixed Signal VLSI Circuits (VLSI Design)
  6. VLSI Fabrication Technology (VLSI Design)

Participation in Faculty Development / STTP / Workshops /Conferences

SNo Title Organization Period Outcome
1. Author Workshop on “scholarly writing and publishing” ASE,Ettimadai April 11, 2018 Research
2. ISTE STTP on CMOS, Mixed Signal and Radio Frequency VLSI Design IIT Kharagpur January 30 – February 4, 2017 Course Plan development for PG
3. National workshop on Signal and Image processing Applications using Xilinx system generator ASE,Ettimadai April 10 – 11, 2014 Research
4. Research Seminar on Emerging Perspectives in Nanoelectronics R&D ASE,Ettimadai September 19, 2014  Research
5. ISTE workshop on Analog Electronics IIT Kharagpur June 4 -14, 2013 PG Elective course
6. Workshop on Research and Project Areas in VLSI Design ASE,Ettimadai January 25, 2013 Research
7. ISTE workshop on Writing Effective Conference Papers IIT Bombay February 18 – 19, 2012 Research
8. Mission 10X workshop ASE & Wipro December 20 – 24, 2010 Innovative Teaching
9. Pre-Conference workshop on Embedded Systems Coimbatore Institute of Technology July 13, 2010 Research
10. Course on Nanotechnology ASE , Ettimadai July 13, 2009 Research
11. Workshop on UltraSparc T2 Processor microarchitecture Sun Microsystems March 29 – 30, 2008 Research
12. Workshop on Optical Communication and Network Design and Modeling Coimbatore Institute of Technology February 4, 2008 Research

Organizing Faculty Development / STTP / Workshops /Conferences

SNo Title Organization Period Outcome
1. National Conference on Recent Trends in Communication and Signal Processing RTCSP’09 ASE , Ettimadai April 7, 2009 Research
2. Student Project Contest ASE ,Ettimadai February 29, 2008 Practical knowledge and Innovation

Academic Research – PG Projects

SNo Name of the Scholar Programme Specialization Duration Status
1. Akella Krishna Vamsi VLSI Design Low Power VLSI 2018-19 Ongoing
2. LachiReddy Dhanunjay VLSI Design Low Power VLSI 2018-19 Ongoing
3. Nithya J VLSI Design Low Power VLSI 2018-19 Ongoing
4. Kosanam Manikanth VLSI Design Static Timing Analysis 2017-18 Completed
5. Mukkamala Venkata Durga Pavan VLSI Design Low Power VLSI 2017-18 Completed
6. Sreenath K VLSI Design Static Timing Analysis 2016-17 Completed
7. Haritha H VLSI Design Low Power VLSI 2016-17 Completed
8. Samarshekar R VLSI Design Static Timing Analysis 2015-16 Completed
9. Prem Lal Paleri VLSI Design VLSI CAD 2014-15 Completed

Research Expertise

  • As of July 2021 the number of students working at various levels under his supervision are:
    • M.Tech – 3 (Static Timing Analysis and Hardware Trojan Detection)
    • B.Tech – 2 (IOT, VLSI)

PG Projects

  • A MUX based Latch Technique for Hardware Trojan Detection
  • Hardware Trojan Detection using Ring Oscillator
  • Flip Flop Based Approach for Logic Encryption Techniques
  • An Approach for Statistical Parameter Estimation and Test pattern Generation
  • Power and Area Efficient Booth Multiplier
  • MAC Unit design and its impact on a Trained Neural Network
  • Hybrid Adder Design for High Speed Applications
  • Power and Delay Efficient ALU using Vedic Techniques
  • An Efficient Booth Multiplier using Probabilistic Approach
  • An Efficient Linear Pipeline Circuit with Optimal Power Delay Product using Soft Edge Flip flops
  • Analytical Modeling of Logic Resource Utilization for Early Stage FPGA Architecture Development
  • Statistical Static Timing Analysis Using Parallel Processing of Timing Graphs
  • Design And Implementation of 1D Discrete Multiwavelet Transform For Infrasound Classification
  • Statistical Timing Analysis Using Probabilistic Approaches
  • Decomposition And Synthesis of XOR Based Logic Circuits For LUT Based FPGAs
  • Probabilistic Activity Estimator For4-input LUT Based FPGA Circuits
  • Data Flow Transformation for Optimization of Digital/DSP Circuits
  • Design of an Optimized Double Precision Floating Point Divider Using Cache Memory and a Multiplier
  • FPGA Implementation of Low Density Parity Check Code Decoder

UG Projects

  • FPGA Implementation of Power and Area Efficient 32 bit MAC Unit
  • A Signed Vedic Multiplier using Redundant Binary Representation
  • Hardware Trojan Detection using Supervised Machine Learning
  • Development of a System to measure Hemoglobin non-invasively
  • Low Delay VLSI Architecture Design for Logarithmic Multiplication
  • A Low Power Cubic Computation Unit using Vedic Techniques
  • Design of Low power Binary Square rooter using Reversible Logic
  • Design of Power Efficient Approximate Multipliers
  • FPGA Implementation of Low power LNS Arithmetic Unit by LUT Partitioning
  • A Comparative analysis on Static and Statistical Timing Techniques
  • An Efficient FIR Filter Design Using Common Sub Expression Elimination Method
  • Multimode Floating Point Adder and Multiplier
  • Power Estimation of Combinational Circuits Using Spatial Correlation

Teaching

  • Electronic Circuits
  • VLSI Technology
  • Digital IC Design
  • VLSI Design
  • VLSI System Design
  • Linear Integrated Circuits
  • Static Timing Analysis
  • Solid State Devices
  • Semiconductor Memory Design

 

Publications

Journal Article

Year : 2021

Hardware Realization of Low power and Area Efficient Vedic MAC in DSP Filters

Cite this Research Publication : D. S. Manikanta, K. S. S. Ramakrishna, M. Giridhar, N. Avinash, T. Srujan and R. S. R, "Hardware Realization of Low power and Area Efficient Vedic MAC in DSP Filters," 2021 5th International Conference on Trends in Electronics and Informatics (ICOEI), 2021, pp. 46-50, doi: 10.1109/ICOEI51242.2021.9453041.

Publisher : 2021 5th International Conference on Trends in Electronics and Informatics (ICOEI)

Year : 2021

A Low Power Signed Redundant Binary Vedic Multiplier

Cite this Research Publication : C. Mahitha, S. C. S. Ayyar, S. D. B, A. Othayoth and R. S R, "A Low Power Signed Redundant Binary Vedic Multiplier," 2021 5th International Conference on Trends in Electronics and Informatics (ICOEI), 2021, pp. 76-81, doi: 10.1109/ICOEI51242.2021.9453032.

Publisher : 2021 5th International Conference on Trends in Electronics and Informatics (ICOEI)

Year : 2021

Design of Combinational Arithmetic Circuits using Quantum Dot Cellular Automata

Cite this Research Publication : S. Prasanna A, B. Madhava Reddy and R. S R, "Design of Combinational Arithmetic Circuits using Quantum Dot Cellular Automata," 2021 5th International Conference on Trends in Electronics and Informatics (ICOEI), 2021, pp. 117-122, doi: 10.1109/ICOEI51242.2021.9453069.

Publisher : 2021 5th International Conference on Trends in Electronics and Informatics (ICOEI)

Year : 2021

Hardware Trojan Detection using Ring Oscillator

Cite this Research Publication : D. S, R. S. R and N. D. M, "Hardware Trojan Detection using Ring Oscillator," 2021 6th International Conference on Communication and Electronics Systems (ICCES), 2021, pp. 362-368, doi: 10.1109/ICCES51350.2021.9488935.

Publisher : 6th International Conference on Communication and Electronics Systems (ICCES)

Year : 2020

A Low Delay Architecture for Logarithmic Multiplication

Cite this Research Publication : P. Kumar Kssrb, N., S. Shantan, S., P., V., B. R., and Ramesh S. R., “A Low Delay Architecture for Logarithmic Multiplication”, 2020 4th International Conference on Trends in Electronics and Informatics (ICOEI)(48184). 2020.

Publisher : International Conference on Trends in Electronics and Informatics (ICOEI)(48184)

Year : 2019

Low Power Cubic Computation Unit Using Vedic Sutras

Cite this Research Publication : P. Aatmica, Ranjith, V., Nimalsurya, I., and Ramesh S. R., “Low Power Cubic Computation Unit Using Vedic Sutras”, IOP Conference Series: Materials Science and Engineering, vol. 561, p. 012114, 2019.

Publisher : IOP Publishing

Year : 2018

Statistical Viability Analysis and Optimization through Gate Sizing

Cite this Research Publication : K. Sreenath and Ramesh S. R., “Statistical Viability Analysis and Optimization through Gate Sizing”, Lecture Notes in Electrical Engineering, vol. 475, pp. 149-155, 2018.

Publisher : Springer, Singapore

Year : 2017

Design of an Enhanced Array Based Approximate Arithmetic Computing Model for Multipliers and Squarers

Cite this Research Publication : H. Haritha and Ramesh S. R., “Design of an Enhanced Array Based Approximate Arithmetic Computing Model for Multipliers and Squarers”, 2017 14th IEEE India Council International Conference (INDICON). 2017.

Publisher : 2017 14th IEEE India Council International Conference (INDICON)

Year : 2016

Improved Statistical Static Timing Analysis Using Refactored Timing Graphs

Cite this Research Publication : Ramesh S. R. and Jayaparvathy, R., “Improved Statistical Static Timing Analysis Using Refactored Timing Graphs”, Journal of Computational and Theoretical Nanoscience, vol. 13, pp. 8879-8884, 2016.

Publisher : Journal of Computational and Theoretical Nanoscience

Year : 2015

Probabilistic activity estimator and timing analysis for LUT based circuits

Cite this Research Publication : Ramesh S. R. and Jayaparvathy, R., “Probabilistic activity estimator and timing analysis for LUT based circuits”, International Journal of Applied Engineering Research, vol. 10, pp. 33238-33242, 2015.

Publisher : Research India Publications

Year : 2015

Early Stage FPGA Architecture Development by Exploiting Dependence on Logic density

Cite this Research Publication : P. L. Paleri and Ramesh S. R., “Early Stage FPGA Architecture Development by Exploiting Dependence on Logic density”, International Journal Of Applied Engineering Research, vol. 10, no. 11, pp. 28889-28902, 2015.

Publisher : International Journal Of Applied Engineering Research

Year : 2014

A Survey of SSTA Techniques with Focus on Accuracy and Speed

Cite this Research Publication : Bhaghath P J,Ramesh S R "A Survey of SSTA Techniques with Focus on Accuracy and Speed" , published in the International Journal of Computer Applications (0975 – 8887), Volume 89 – No.7, March 2014.

Publisher : International Journal of Computer Applications

Year : 2012

Toggle Rate Estimation Technique for 4-Input LUT based FPGA Circuits

Cite this Research Publication : Anju.P.J, Ramesh.S.R “Toggle Rate Estimation Technique for 4 input LUT based FPGA circuits” in International Journal of Engineering Research and Applications vol.2,no.3 pp 198-203,May-June2012

Publisher : International Journal of Engineering Research and Applications

Year : 2012

An Approach towards Logic Synthesis by Functional Decomposition

Cite this Research Publication : Athira .P.V, Ramesh.S.R “ An Approach towards Logic Synthesis by Functional Decomposition” in International Journal of Engineering Research and Applications vol.2,no.3 pp 324-330,May-June2012

Publisher : International Journal of Engineering Research and Applications

Conference Paper

Year : 2021

Hardware Trojan Detection using Supervised Machine Learning

Cite this Research Publication : G. M, k. S. Harsha, J. Nikhil, M. S. Eswar and R. S R, "Hardware Trojan Detection using Supervised Machine Learning," 2021 6th International Conference on Communication and Electronics Systems (ICCES), 2021, pp. 1451-1456, doi: 10.1109/ICCES51350.2021.9489081.

Publisher : 2021 6th International Conference on Communication and Electronics Systems (ICCES)

Year : 2017

Toggle Rate Estimation and Glitch Analysis on Logic Circuits

Cite this Research Publication : Ramesh S. R. and Jayaparvathy, R., “Toggle Rate Estimation and Glitch Analysis on Logic Circuits”, 2017 IEEE International Workshop On Integrated Power Packaging (IWIPP). 2017.

Publisher : 2017 IEEE International Workshop On Integrated Power Packaging (IWIPP)

Year : 2014

A comparison on timing analysis using probabilistic approaches

Cite this Research Publication : B. P. J and Ramesh S. R., “A comparison on timing analysis using probabilistic approaches”, in Communications and Signal Processing (ICCSP), 2014 International Conference on, 2014.


Publisher : ICCSP

Year : 2012

Area and speed aware Decomposition of Logic circuits for Look Up Table based FPGAs

Cite this Research Publication : Ramesh S. R. and P.V, A., “Area and speed aware Decomposition of Logic circuits for Look Up Table based FPGAs”, in Third International Conference on Intelligent Information Systems and Management(IISM), RVS College of Engineering and Technology, Coimbatore, 2012.

Publisher : RVS College of Engineering and Technology

Year : 2010

Online Noise Reduction Technique for Mobile Communication Using LABVIEW

Cite this Research Publication : M. .B and Ramesh S. R., “Online Noise Reduction Technique for Mobile Communication Using LABVIEW”, in International Conference on Embedded Systems (ICES) , by EEE Department, Coimbatore Institute of Technology, Coimbatore , 2010.

Publisher : Coimbatore Institute of Technology

Year : 2010

Design and Implementation of an Optimized Double Precision Floating Point Divider using Cache Memory

Cite this Research Publication : S. .K and Ramesh S. R., “Design and Implementation of an Optimized Double Precision Floating Point Divider using Cache Memory”, in International Conference on Embedded Systems (ICES 2010) , EEE Department, Coimbatore Institute of Technology, Coimbatore, 2010.

Publisher : Coimbatore Institute of Technology

Year : 2010

Cross talk Effects on Mixed Signal CMOS ICs

Cite this Research Publication : A. Baby, Raju, R., and Ramesh S. R., “Cross talk Effects on Mixed Signal CMOS ICs”, in International Conference on Advances in Information Communication Technology and VLSI Design , 2010.

Publisher : International Conference on Advances in Information Communication Technology and VLSI Design

Conference Proceedings

Year : 2020

Power and Delay Efficient ALU Using Vedic Multiplier

Cite this Research Publication : D. Lachireddy and Ramesh S. R., “Power and Delay Efficient ALU Using Vedic Multiplier”, Advances in Electrical and Computer Technologies. Springer Singapore, Singapore, 2020.

Publisher : Springer Singapore

Year : 2020

Area and Power Efficient 64-Bit Booth Multiplier

Cite this Research Publication : P. Kartheek Somayajulu and Ramesh S. R., “Area and Power Efficient 64-Bit Booth Multiplier”, 2020 6th International Conference on Advanced Computing and Communication Systems (ICACCS). 2020.

Publisher : 2020 6th International Conference on Advanced Computing and Communication Systems (ICACCS)

Year : 2020

A Novel Approach for Statistical Parameter Estimation and Test Pattern Generation

Cite this Research Publication : N. G.S. and Ramesh S. R., “A Novel Approach for Statistical Parameter Estimation and Test Pattern Generation”, 2020 4th International Conference on Trends in Electronics and Informatics (ICOEI)(48184). 2020.

Publisher : 2020 4th International Conference on Trends in Electronics and Informatics (ICOEI)(48184)

Year : 2020

Cloud Storage Optimization for Video Surveillance Applications

Cite this Research Publication : R. Marceline, Akshaya, S. R., Athul, S., Raksana, K. L., and Ramesh S. R., “Cloud Storage Optimization for Video Surveillance Applications”, 2020 Third International Conference on Smart Systems and Inventive Technology (ICSSIT). 2020.

Publisher : 2020 Third International Conference on Smart Systems and Inventive Technology (ICSSIT)

Year : 2019

A Low Power Binary Square rooter using Reversible Logic

Cite this Research Publication : A. Krishna, Raj, L. S. Anusree, Priyadarsini, G., Raghul, S., and Ramesh S. R., “A Low Power Binary Square rooter using Reversible Logic”, 2019 5th International Conference on Advanced Computing and Communication Systems, ICACCS 2019. Institute of Electrical and Electronics Engineers Inc., pp. 619-623, 2019.

Publisher : Institute of Electrical and Electronics Engineers Inc.,

Year : 2019

An efficient design of 16 bit MAC unit using vedic mathematics

Cite this Research Publication : A. S. Krishna Vamsi and S. R. Ramesh, "An Efficient Design of 16 Bit MAC Unit using Vedic Mathematics," 2019 International Conference on Communication and Signal Processing (ICCSP), Chennai, India, 2019, pp. 319-322. doi: 10.1109/ICCSP.2019.8697985.

Publisher : Institute of Electrical and Electronics Engineers Inc.

Year : 2019

Design of Delay Efficient Hybrid Adder for High Speed Applications

Cite this Research Publication : J. Nithya and Ramesh S. R., “Design of Delay Efficient Hybrid Adder for High Speed Applications”, 2019 5th International Conference on Advanced Computing and Communication Systems, ICACCS 2019. Institute of Electrical and Electronics Engineers Inc., pp. 374-378, 2019.

Publisher : Institute of Electrical and Electronics Engineers Inc.,

Year : 2019

Artificial neural network model for arrival time computation in gate level circuits

Cite this Research Publication : Ramesh S R, Jayaparvathy R “Artificial Neural Network Model for Arrival Time Computation in Gate Level Circuits”, Automatika ,Vol.60,no.3.pp.360-367,May 2019

Publisher : Automatika

Year : 2018

FPGA Implementation of Power Efficient Approximate Multipliers

Cite this Research Publication : K. G. Hemamithra, S Priya, L., Lakshmirajan, K., Mohanrai, R., and Ramesh S. R., “FPGA Implementation of Power Efficient Approximate Multipliers”, 2018 3rd IEEE International Conference on Recent Trends in Electronics, Information Communication Technology (RTEICT). 2018.

Publisher : 2018 3rd IEEE International Conference on Recent Trends in Electronics, Information Communication Technology

Year : 2018

Statistical Viability Analysis and Optimization through Gate Sizing

Cite this Research Publication : Sreenath, K., Ramesh, S.R. (2018). Statistical Viability Analysis and Optimization Through Gate Sizing. In: Bhattacharyya, S., Gandhi, T., Sharma, K., Dutta, P. (eds) Advanced Computational and Communication Paradigms. Lecture Notes in Electrical Engineering, vol 475. Springer, Singapore

Publisher : Springer, Singapore

Year : 2018

An Efficient Booth Multiplier Using Probabilistic Approach

Cite this Research Publication : M. V. Durga Pavan and Ramesh S. R., “An Efficient Booth Multiplier Using Probabilistic Approach”, Proceedings of the 2018 IEEE International Conference on Communication and Signal Processing, ICCSP 2018. Institute of Electrical and Electronics Engineers Inc., pp. 365-368, 2018.

Publisher : Institute of Electrical and Electronics Engineers Inc.,

Year : 2018

Design of Soft Edge Flip Flops for the Reduction of Power Delay Product in Linear Pipeline Circuits

Cite this Research Publication : K. Manikanth and Ramesh S. R., “Design of Soft Edge Flip Flops for the Reduction of Power Delay Product in Linear Pipeline Circuits”, Proceedings of the 2018 IEEE International Conference on Communication and Signal Processing, ICCSP 2018. Institute of Electrical and Electronics Engineers Inc., pp. 148-151, 2018.

Publisher : Proceedings of the 2018 IEEE International Conference on Communication and Signal Processing, ICCSP 2018

Year : 2017

VLSI Implementation of LNS Arithmetic Unit by LUT Partitioning

Cite this Research Publication : vV. Vinod, Eswar, K., Vishnuvardhan, P., Srikanth, G., and Ramesh S. R., “VLSI Implementation of LNS Arithmetic Unit by LUT Partitioning”, 2017 International Conference on Advances in Computing, Communications and Informatics (ICACCI). pp. 2241-2245, 2017.

Publisher : 2017 International Conference on Advances in Computing, Communications and Informatics (ICACCI)

Year : 2014

An Efficient FIR Filter Design using CSE Method

Cite this Research Publication : Ramesh S. R., priya.V, S., Reddy, N. S., Mogi, V. M. Abitha, and .S.Sakthi, K., “An Efficient FIR Filter Design using CSE Method”, International Conference on Intelligent Engineering Systems . Department of ECE, Easa College of Engineering and Technology, Coimbatore., 2014.

Publisher : International Conference on Intelligent Engineering Systems

Year : 2012

Toggle rate estimation technique for FPGA circuits considering spatial correlation

Cite this Research Publication : P. Ja Anju and Ramesh S. R., “Toggle rate estimation technique for FPGA circuits considering spatial correlation”, 2012 3rd International Conference on Computing, Communication and Networking Technologies, ICCCNT 2012. Coimbatore, Tamilnadu, 2012.

Publisher : 2012 3rd International Conference on Computing, Communication and Networking Technologies

Year : 2011

Dataflow Transformation for Optimization of Digital/DSP Circuits

Cite this Research Publication : Ramesh S. R., Dr. Bala Tripura Sundari B., and .N, N., “Dataflow Transformation for Optimization of Digital/DSP Circuits”, Third National Conference on Recent Trends in Communication, Computation & Signal Processing organized by Department of ECE,Amrita School of Engineering, Ettimadai . 2011.

Publisher : Amrita School of Engineering

Year : 2010

VLSI Implementation of Asynchronous CDMA using Matched Filter

Cite this Research Publication : S. Manojna.D, .S, S. S., and Ramesh S. R., “VLSI Implementation of Asynchronous CDMA using Matched Filter”, International Conference on Communication and Computational Intelligence. 2010.

Publisher : International Conference on Communication and Computational Intelligence

Year : 2010

A Systolic Architecture for Efficient Colour to Grey Scale Conversion and Reconstruction

Cite this Research Publication : Ramesh S. R., Scaria, A., and Nath.D, B., “A Systolic Architecture for Efficient Colour to Grey Scale Conversion and Reconstruction”, International Conference on Emerging Trends in Signal Processing and VLSI Design. Department of ECE, Guru Nanak Engineering College, Ibrahimpatnam., 2010.

Publisher : Guru Nanak Engineering College

Year : 2010

Speech CODEC for Single Channel Applications Using LABVIEW

Cite this Research Publication : M. .B and Ramesh S. R., “Speech CODEC for Single Channel Applications Using LABVIEW”, Second National Conference on Recent Trends in Communication, Computation & Signal Processing(RTCSP2010). Department of ECE, Amrita School of Engineering , Ettimadai, 2010.

Publisher : Amrita School of Engineering , Ettimadai

Year : 2010

On-chip FPGA Implementation of OFDM Receiver Components

Cite this Research Publication : Ramesh S. R., .S.M, L., and .T, A., “On-chip FPGA Implementation of OFDM Receiver Components”, First International Conference on Emerging Trends in Signal Processing and VLSI Design. Department of ECE, Guru Nanak Engineering College, Ibrahimpatnam, 2010.

Publisher : Guru Nanak Engineering College

Year : 2010

Design of an Area Optimized Double Precision Floating Point Divider on FPGA

Cite this Research Publication : Ramesh S. R. and .K, S., “Design of an Area Optimized Double Precision Floating Point Divider on FPGA”, International Conference on Intelligent Information Systems & Management-(IISM10). RVS College of Engineering and Technology, Coimbatore, 2010.

Publisher : RVS College of Engineering and Technology

Year : 2009

FPGA Implementation of a Low Density Parity Check Code Decoder using Min Sum Algorithm

Cite this Research Publication : R. .S and Ramesh S. R., “FPGA Implementation of a Low Density Parity Check Code Decoder using Min Sum Algorithm”, National Conference on Emerging trends in Communication Engineering. Department of ECE, Trichy Engineering College, Trichy, 2009.

Publisher : Trichy Engineering College

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