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Kirti-S-Pande_asst-professor_ece_bengaluru_campus

Kirti S. Pande

Assistant Professor (Sr.Gr), Department of Electronics and Communication, School of Engineering, Bengaluru

Qualification: BE, M.Tech.
sp_kirti@blr.amrita.edu
Research Interest: Digital Design, GALS Structures, Memory Design – SRAM Structure, Processor and Microcontroller Based Circuits, Very Large Scale Integration (VLSI) Design, VLSI Design: MOSFET Based and Verilog Based Architectures

Bio Publications Professional Appointments Major Research Interests Awards Courses Taught Student Guidance
Bio

Kirti S. Pande currently serves as Assistant Professor (Sr.Gr) at the Department of Electronics and Communication, Amrita School of Engineering, Bengaluru.

Education

  • M. Tech. in VLSI Design (2010)
    From: Amrita School of Engineering, Bengaluru, Karnataka, Amrita Vishwa Vidyapeetham
  • PG Diploma in VLSI Design (2002)
    From: CDAC, Bengaluru, Karnataka
  • B.E. in Electronics Engineering (2001)
    From: Priyadarshini College of Engineering, Nagpur, Nagpur University, Maharashtra.
Publications

Journal Article

Year : 2012

Low Power GALS Interface Implementation with Stretchable Clocking Scheme

Cite this Research Publication : C. Anju and Pande, K. S., “Low Power GALS Interface Implementation with Stretchable Clocking Scheme”, IJCSI International Journal of Computer Science Issues, , vol. 9, no. 4, 2012.

Publisher : Citeseer

Year : 2012

Design, Implementation and Performance Analysis of an Integrated Vedic Multiplier Architecture

Cite this Research Publication : S. Ramachandran and Pande, K. S., “Design, Implementation and Performance Analysis of an Integrated Vedic Multiplier Architecture”, International Journal of Computational Engineering Research, vol. 2, pp. 697–703, 2012.

Publisher : International Journal of Computational Engineering Research

Year : 2012

Design and Performance Analysis of Poly Synchronous DTI FIFO

Cite this Research Publication : A. C. and Pande, K. S., “Design and Performance Analysis of Poly Synchronous DTI FIFO”, Global Journal of Engineering & Applied Sciences, 2012. Rising Research Journal Publication., vol. 2, no. 1, pp. 72-74, 2012.

Publisher : Rising Research Journal Publication

Conference Paper

Year : 2021

Electromigration and IR Voltage Drop Reduction Technique on DDR Memory Block Using Power Grid Augmentation

Cite this Research Publication : A. Marni and K. S. Pande, "Electromigration and IR Voltage Drop Reduction Technique on DDR Memory Block Using Power Grid Augmentation," 2021 5th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), 2021

Publisher : IEMENTech

Year : 2021

Strong Single-Arm Latch Comparator with Reduced Power Consumption

Cite this Research Publication : G. Jithin, G. B. V. S. V. Prasad, J. V. N. S. Krishna and K. S. Pande, "Strong Single-Arm Latch Comparator with Reduced Power Consumption," 2021 Fourth International Conference on Electrical, Computer and Communication Technologies (ICECCT), 2021

Publisher : ICECCT

Year : 2021

MTCMOS 8T SRAM Cell with Improved Stability and Reduced Power Consumption

Cite this Research Publication : S. Anusha, B. S. Nikhil, K. S. Manoj and K. S. Pande, "MTCMOS 8T SRAM Cell with Improved Stability and Reduced Power Consumption," 2021 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), 2021

Publisher : IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)

Year : 2020

Speed Improvement in SRAM Cell Using Transmission Gates

Cite this Research Publication : P. Swetha, P Meghana, S., Charisma, J., and Pande, K. S., “Speed Improvement in SRAM Cell Using Transmission Gates”, in 2020 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), Udupi, India, 2020.

Publisher : 2020 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)

Year : 2020

Compressor Using Full Swing XOR Logic Gate

Cite this Research Publication : S. Harsha Bandarupalli, Bandi, B. Pavan Kaly, Boggula, R. Kumar Redd, and Pande, K. S., “Compressor Using Full Swing XOR Logic Gate”, in 2020 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), Udupi, India, 2020.

Publisher : 2020 IEEE International Conference on Distributed Computing

Year : 2020

Error Detection and Correction Using RP SEC-DED

Cite this Research Publication : N. Farheen and Pande, K. S., “Error Detection and Correction Using RP SEC-DED”, in 2020 4th International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech), Kolkata, India, 2020.

Publisher : 2020 4th International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech)

Year : 2020

Low Power Rail to Rail D Flip-Flop Using Current Mode Logic Structure

Cite this Research Publication : S. Mutukuri and Pande, K. S., “Low Power Rail to Rail D Flip-Flop Using Current Mode Logic Structure”, in 2020 4th International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech), Kolkata, India, 2020.

Publisher : 2020 4th International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech)

Year : 2019

SQAC Using Folding-Merging Based Squarer

Cite this Research Publication : H. M., K., N., P., M., and Pande, K. S., “SQAC Using Folding-Merging Based Squarer”, in 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA), Coimbatore, India, 2019.

Publisher : 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA),

Year : 2019

Multiplier Using NAND Based Compressors

Cite this Research Publication : T. Satish and Pande, K. S., “Multiplier Using NAND Based Compressors”, in 2019 3rd International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech), Kolkata, India, 2019.

Publisher : 2019 3rd International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech)

Year : 2019

Critical Path Delay Improvement in Logic Circuit Operated at Subthreshold Region

Cite this Research Publication : L. Mohit Dhirubhai and Pande, K. S., “Critical Path Delay Improvement in Logic Circuit Operated at Subthreshold Region”, in 2019 International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, 2019.

Publisher : 2019 International Conference on Communication and Electronics Systems (ICCES)

Year : 2019

NMOS Only Schmitt Trigger Based SRAM Cell

Cite this Research Publication : R. Adithi, Dambal, S., and Pande, K. S., “NMOS Only Schmitt Trigger Based SRAM Cell”, in 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA), Coimbatore, India, 2019.

Publisher : 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA),

Year : 2018

All Digital Phase Locked Loop for Low Frequency Applications

Cite this Research Publication : P. R. Bissa and Pande, K. S., “All Digital Phase Locked Loop for Low Frequency Applications”, in 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI), Bangalore, India, 2018.

Publisher : 2018 International Conference on Advances in Computing

Year : 2018

4-bit Counter using High-Speed Low-Voltage CML D-Flipflops

Publisher : International Conference on Communication and Electronics Systems (ICCES) 2018

Year : 2017

Leakage Reduction in DT8T SRAM Cell Using Body Biasing Technique

Cite this Research Publication : R. Suthar, Pande, K. S., and Murty, N. S., “Leakage Reduction in DT8T SRAM Cell Using Body Biasing Technique”, in 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Bhopal, India, 2017.

Publisher : 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)

Year : 2016

Dual-threshold single-ended Schmitt-Trigger based SRAM cell

Cite this Research Publication : D. Sreenivasan, Purushothaman, D., Pande, K. S., and Dr. N.S. Murty, “Dual-threshold single-ended Schmitt-Trigger based SRAM cell”, in 2016 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), 2016.

Publisher : 2016 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)

Year : 2015

Subthreshold voltage to supply voltage level shifter using modified revised wilson current mirror

Cite this Research Publication : J. Parimala, Priyanka, K., Kaumudi, L. S., Pande, K. S., and Dr. N.S. Murty, “Subthreshold voltage to supply voltage level shifter using modified revised wilson current mirror”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015, 2015.

Publisher : 2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015

Year : 2015

Stability investigation for 1R-2W and 2R-2W Register File SRAM bit cell using FinFET in subthreshold region

Cite this Research Publication : S. Mohan, Pande, K. S., and Dr. N.S. Murty, “Stability investigation for 1R-2W and 2R-2W Register File SRAM bit cell using FinFET in subthreshold region”, in 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, 2015.

Publisher : 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015

Year : 2015

SRAM cell with improved stability and reduced leakage current for subthreshold region of operation

Cite this Research Publication : P. Sreelakshmi, Pande, K. S., and Dr. N.S. Murty, “SRAM cell with improved stability and reduced leakage current for subthreshold region of operation”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015, 2015.

Publisher : 2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015

Year : 2015

A memory architecture using linear and nonlinear feedback shift registers for data security

Cite this Research Publication : J. Jose, Pande, K. S., and Dr. N.S. Murty, “A memory architecture using linear and nonlinear feedback shift registers for data security”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015, 2015.

Publisher : 2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015

Professional Appointments
Year Affiliation
July 2006 to till Date Amrita School of Engineering, Bengaluru, Karnataka
August 2005 to June 2006 Dayananda Sagar College of Engineering, Bengaluru, Karnataka
September 2002 to May 2003 M. G. M’s College of Engineering, Nanded, Maharashtra
Major Research Interests
  • VLSI Design: MOSFET Based and Verilog Based Architectures, Digital Design, Memory Design – SRAM Structure, Processor and Microcontroller Based Circuits, GALS Structures.
Awards

Certificates, Awards & Recognitions

  • Received best paper award for paper: D. Sreenivasan, D. Purushothaman, K. S. Pande and N. S. Murty, “Dual-threshold single-ended Schmitt-Trigger based SRAM cell,” 2016 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), Chennai, 2016, pp. 1-4, doi: 10.1109/ICCIC.2016.7919674
  • Reviewed technical papers for IETE Journal
Courses Taught
  • VLSI Design, VLSI System Design, Solid State Devices, Physics of MOS Devices, CMOS Integrated Circuits, System on Chip, Semiconductor Memory Design, Digital Systems and Design, Circuit Theory, Network Theory, Microcontroller, Microprocessor, Basic Electronics
Student Guidance

Undergraduate Students

Sl. No. Name of the Student(s) Topic Status – Ongoing/Completed Year of Completion
Divisha Singhani, U. S. Aarathi, Deeksha Design and Analysis of Level Shifter Ongoing 2022
Yarra Kaveri, B. Udya Kumar, Bharani Design and Analysis of Synchronous Counter Ongoing 2022
Anusha, Nikhil M., Manoj Sai Design and Analysis of 7T SRAM Cell Completed 2021
Jithin, J.V. V. S. Satya Prasad, Sai Krishna Design and analysis of high speed comparator Completed 2021
P Swetha, P Sai Meghana, Jonnala Charisma Speed Improvement in SRAM Cell Using

Transmission Gates

 Completed 2020
Sri Harsha Bandarupalli, Bala Pavan Kalyan Bandi, Rahul Kumar Reddy Boggula Compressor Using Full Swing XOR

Logic Gate

 Completed 2020
H. Sharath, A. Nithenn, I. Srikar Design and Implementation of Sobol Sequence Generators Completed 2020
R. Adithi, Soumya Dambal NMOS Only Schmitt Trigger Based SRAM Cell Completed 2019
 Hemanth M., Naveen K., Mohan P.  SQAC Using Folding-Merging Based Squarer Completed 2019
10. Manoj, Nikhil Adaptive Feedback Equalization Completed 2018
11. Nikhila Kotra, Ramya Kosaraju, Rohitha Complex Square Root Computation using Bakhshali Algorithm Completed 2018
12. N. Sai Anuhya, Sagarika Naik , K. Kirtisha Low Power Architecture for 3-Level Data Cache Module using Write Buffer Completed 2017
13. Devika P, Divya K. S. Mohana Bhavani Design of a Single Ended Schmitt-Trigger based 11T SRAM cell using
Multi-threshold CMOS Technology		 Completed 2016
14. K.Priyanka,

P. Harshitha,

Pavan Tej

 Low power D8T SRAM cell using DTMOS Completed 2016
15. Nikhilesh M., Viswas P. Implementation of 8T SRAM Cell Using FinFET Completed 2015
16. K.Priyanka

L. Seetha Kaumudi J.Parimala

 Subthreshold Voltage to Supply Voltage Level Shifter Using Modified Revised Wilson Current Mirror Completed 2015

Postgraduate Students

Sl. No. Name of the Student(s) Topic Status – Ongoing/Completed Year of Completion
1 Thanga Dharsni Deisgn of Pipelining Architecture for RISC machine Ongoing 2020
2 Amareshwar. M Electro Migration and IR Voltage Drop Reduction Technique on DDR Block Using Power Grid Augmentation Completed 2021
3 Mutukuri Sri Vatsa Low Power Rail to Rail D Flip-Flop Using Current Mode Logic Structure Completed 2020
4 Nadia Farheen Error Detection and Correction Using RP SEC-DED Completed 2020
5 Mohit Dhirubhai Critical Path Delay Improvement in Logic Circuit Operated at Subthreshold Region Completed 2019
6 Tella Satish Multiplier Using NAND Based Compressors Completed 2019
7 Pradyuman R. Bissa All Digital Phase Locked Loop for Low Frequency Applications Completed 2018
8 Resham Singh 4-bit Counter Using High-Speed Low-Voltage CML D-Flipflops Completed 2018
9 Rajani Suthar Leakage Reduction in DT8T SRAM Cell Using Body Biasing Technique Completed 2017
10 Hari Prasath Operation Aware SRAM Cache line for Low Power Cache

using Multi Threshold CMOS Technique

 Completed 2017
11 Aarathy V. Nair Performance of Multiport FinFET Based SRAM Cell Designed using Different Read Buffers Operated in Near-threshold Region Completed 2016
12 P. Sreelakshmi SRAM cell with improved stability and reduced leakage current for subthreshold region of operation Completed 2015
13 Jismi Jose A memory architecture using linear and nonlinear feedback shift registers for data security Completed 2015
14 Sreyas Mohan Stability investigation for 1R-2W and 2R-2W Register File SRAM bit cell using FinFET in subthreshold region Completed 2014
15 Anju C. Low Power GALS Implementation with Stretchable Clocking Scheme Completed 2012
16 Pratibha P.  Implementation of GALS Chip Multiprocessor with Flexibly Configurable Low Latency Interconnect Completed 2011
17 Ramachandran S.  Design, Implementation and Performance Analysis of an Integrated Vedic Multiplier Architecture Completed 2011
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