Year : 2021
A QCA based improvised TRNG design for the implementation of secured Nano Communication protocol for ATM services
Cite this Research Publication : Arindam Sadhu, Kunal Das, Debashis De, Maitreyi R. Kanjilal, and Dr. Pritam Bhattacharjee, “A QCA based improvised TRNG design for the implementation of secured Nano Communication protocol for ATM services”, in 3rd International Conference on Computational Advancement in Communication Circuits and Systems (Accepted & Presented, Scopus), 2021.
Publisher : 3rd International Conference on Computational Advancement in Communication Circuits and Systems (Accepted & Presented, Scopus)
Year : 2021
Study of Machine Learning Techniques to Mitigate Fraudulent Transaction in Credit Cards
Cite this Research Publication : Sayan Sikder, Shubhasree Sarkar, Eric G. Varghese, and Dr. Pritam Bhattacharjee, “Study of Machine Learning Techniques to Mitigate Fraudulent Transaction in Credit Cards”, in 3rd International Conference on Machine Intelligence and Signal Processing (Accepted, Scopus), 2021.
Publisher : 3rd International Conference on Machine Intelligence and Signal Processing (Accepted, Scopus)
Year : 2020
A Variable Delay Circuit to Develop Identical Rise/Fall Time in the Output
Cite this Research Publication : Dr. Pritam Bhattacharjee and Alak Majumder, “A Variable Delay Circuit to Develop Identical Rise/Fall Time in the Output”, in Computational Advancement in Communication Circuits and Systems (Scopus), Singapore, 2020, pp. 305–312.
Publisher : Springer Singapore
Year : 2018
Data-Dependent Clock Gating approach for Low Power Sequential System
Cite this Research Publication : Dhiraj Sarkar, Dr. Pritam Bhattacharjee, and Alak Majumder, “Data-Dependent Clock Gating approach for Low Power Sequential System”, in MICRO-2018, Bhubaneswar, India (5th International Conference on Microelectronics, Circuits & Systems), 2018, pp. 49–53.
Publisher : MICRO-2018, Bhubaneswar, India (5th International Conference on Microelectronics, Circuits & Systems)
Year : 2017
LECTOR Based Clock Gating for Low Power Multi-Stage Flip Flop Applications
Cite this Research Publication : Dr. Pritam Bhattacharjee, Bipasha Nath, and Alak Majumder, “LECTOR Based Clock Gating for Low Power Multi-Stage Flip Flop Applications”, in International Conference on Electronics, Information, and Communication (ICEIC) (Scopus), 2017, pp. 106-109.
Publisher : International Conference on Electronics, Information, and Communication (ICEIC) (Scopus)
Year : 2017
Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip
Cite this Research Publication : Alak Majumder and Dr. Pritam Bhattacharjee, “Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip”, in 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) (Scopus), Bhopal, India, 2017, pp. 224–228.
Publisher : 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) (Scopus), IEEE
Year : 2016
A 90 nm leakage control transistor based clock gating for low power flip flop applications
Cite this Research Publication : Dr. Pritam Bhattacharjee, Alak Majumder, and Tushar Dhabal Das, “A 90 nm leakage control transistor based clock gating for low power flip flop applications”, in 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS) (Scopus), Abu Dhabi, United Arab Emirates, 2016, pp. 1–4.
Publisher : 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS) (Scopus), IEEE
Year : 2016
LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder
Cite this Research Publication : Dr. Pritam Bhattacharjee and Alak Majumder, “LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder”, in 2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) (Scopus), Gwalior, India, 2016, pp. 250–254.
Publisher : 2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) (Scopus), IEEE
Year : 2016
A register-transfer-level description of synthesizable binary multiplier and binary divider
Cite this Research Publication : Dr. Pritam Bhattacharjee, Arindam Sadhu, and Kunal Das, “A register-transfer-level description of synthesizable binary multiplier and binary divider”, in 2016 International Conference on Microelectronics, Computing and Communications (MicroCom) (Scopus), Durgapur, India, 2016, pp. 1–6.
Publisher : 2016 International Conference on Microelectronics, Computing and Communications (MicroCom) (Scopus), IEEE
Year : 2015
SPICE Modeling and Analysis for Metal Island Ternary QCA Logic Device
Cite this Research Publication : Dr. Pritam Bhattacharjee, Kunal Das, Mallika De, and Debashis De, “SPICE Modeling and Analysis for Metal Island Ternary QCA Logic Device”, in Information Systems Design and Intelligent Applications (Scopus), New Delhi, 2015, pp. 33–41.
Publisher : Information Systems Design and Intelligent Applications (Scopus), Springer India,
Year : 2014
Characterization of Ternary Quantum dot cellular Automata for III-V Materials
Cite this Research Publication : Dr. Pritam Bhattacharjee, Arijit Dey, Das, K., Mallika De, and Debashis De, “Characterization of Ternary Quantum dot cellular Automata for III-V Materials”, in National Conference on Nanoscience and Nanotechnology (NS&NT-2014), 2014.
Publisher : National Conference on Nanoscience and Nanotechnology (NS&NT-2014)