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P-Satish-Kumar_asst-professor_ece_bengaluru_campus

P. Satish Kumar

Asst. Professor (Sr. Gr), Electronics and Communication Engineering, School of Engineering, Bengaluru

Qualification: M.E
p_sathishkumar@blr.amrita.edu
Research Interest: Analog Design, CMOS, Digital Design, Very-Large-Scale Integration (VLSI)

Bio Publications Courses Taught Student Guidance
Bio

P.Sathishkumar currently serves as Assistant Professor (Senior Grade) at the Department of Electronics and Communication Engineering, Amrita School of Engineering, Bengaluru campus. I have more than 14 year of experience in teaching. I have more 20 international conference papers. My current research interest in the VLSI domain improve security for the system design and digital system implementation in FPGA.

Education

  • M.E in VLSI Design
    From: ANNA UNIVERISTY
  • B.E in Electronics and Instrumentation Engineering
    From: Bharathiyar University
Publications

Conference Paper

Year : 2020

Implementation of modified Dual-CLCG Method for Pseudorandom bit Generation

Cite this Research Publication : B. Sunandha and P. Sathish Kumar, “Implementation of modified Dual-CLCG Method for Pseudorandom bit Generation”, in 2020 International Conference on Smart Electronics and Communication (ICOSEC), Trichy, India, 2020.

Publisher : 2020 International Conference on Smart Electronics and Communication (ICOSEC),

Year : 2020

Low Complexity LDPC Error Correction Code for Modified Anderson PUF to Improve its Uniformity

Cite this Research Publication : M. kalya and P. Sathish Kumar, “Low Complexity LDPC Error Correction Code for Modified Anderson PUF to Improve its Uniformity”, in 2020 International Conference on Smart Electronics and Communication (ICOSEC), Trichy, India, 2020.

Publisher : 2020 International Conference on Smart Electronics and Communication (ICOSEC)

Year : 2019

High Speed Error-Detection and Correction Architectures for Viterbi Algorithm Implementation

Cite this Research Publication : K. A Kumar and P. Sathish Kumar, “High Speed Error-Detection and Correction Architectures for Viterbi Algorithm Implementation”, in 2019 3rd International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech), Kolkata, India, 2019.

Publisher : 2019 3rd International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech)

Year : 2018

Pulse based Acyclic Asynchronous Pipelines for Combinational Logic Circuits

Cite this Research Publication : S. Kumar and P. Sathish Kumar, “Pulse based Acyclic Asynchronous Pipelines for Combinational Logic Circuits”, in 2018 International Conference on Computer Communication and Informatics (ICCCI), 2018.

Publisher : 2018 International Conference on Computer Communication and Informatics (ICCCI),

Year : 2018

high-speed-error-detection-and-correction-architectures-for-viterbi-algorithm-implementation/

Cite this Research Publication : A. Kumar Reddy and P. Sathish Kumar, “Performance analysis of 8-point FFT using approximate radix -8 booth multipliter”, in International conference on communication and Electronics System (ICCES-2018), 2018.

Publisher : International conference on communication and Electronics System

Year : 2018

Low power and area efficient error tolerant design for parallel filters

Cite this Research Publication : S. S. and P. Sathish Kumar, “Low power and area efficient error tolerant design for parallel filters”, in ymposium on VLSI Design and Embedded Computing (VDEC’18), co-affiliated with Seventh International Conference on Advances in Computing, Communications and Informatics (ICACCI-2018, PES Institute of Technology, Bengaluru, South Campus, India, 2018.

Publisher : ymposium on VLSI Design and Embedded Computing (VDEC’18), co-affiliated with Seventh International Conference on Advances in Computing, Communications and Informatics (ICACCI-2018

Year : 2018

Implementation of FIR Filter and MAC Unit by using Neural Networks in FPGA

Cite this Research Publication : A. Chauhan and P. Sathish Kumar, “Implementation of FIR Filter and MAC Unit by using Neural Networks in FPGA”, in Symposium on VLSI Design and Embedded Computing (VDEC’18), co-affiliated with Seventh International Conference on Advances in Computing, Communications and Informatics (ICACCI-2018), PES Institute of Technology, Bengaluru, South Campus, India, 2018.

Publisher : Symposium on VLSI Design and Embedded Computing (VDEC’18), co-affiliated with Seventh International Conference on Advances in Computing, Communications and Informatics (ICACCI-2018)

Year : 2016

Security situational aware intelligent road traffic monitoring using UAVs

Cite this Research Publication : R. Reshma, Ramesh, T., and P. Sathish Kumar, “Security situational aware intelligent road traffic monitoring using UAVs”, in 2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA), Bengaluru, India, 2016.

Publisher : International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)

Year : 2015

All digital phase locked loop with input clock fail detector

Cite this Research Publication : T. V. Aswathi and P. Sathish Kumar, “All digital phase locked loop with input clock fail detector”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), Madurai, India, 2015.

Publisher : 2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC),

Year : 2015

Implementation of Viterbi coder for text to speech synthesis

Cite this Research Publication : M. L. Padmesh and P. Sathish Kumar, “Implementation of Viterbi coder for text to speech synthesis”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), Madurai, India, 2015.

Publisher : 2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)

Year : 2015

Security incident management in ground transportation system using UAVs

Cite this Research Publication : Ra Reshma, Ramesh, T. Ka, and P. Sathish Kumar, “Security incident management in ground transportation system using UAVs”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015, 2015.

Publisher : 2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015

Year : 2015

Design and implementation of fast floating point multiplier unit

Cite this Research Publication : N. V. Sunesh and P. Sathish Kumar, “Design and implementation of fast floating point multiplier unit”, in 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, 2015.

Publisher : 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015

Patents

Year : 2013

JTAG Architecture with Multi-Security Level

Cite this Research Publication : P. Ajay Kumar, P. Kumar, S., and Patwa, A., “JTAG Architecture with Multi-Security Level”, U.S. Patent 1925/CHE/2013 2013.

Publisher : Number 1925/CHE/2013 , India

Courses Taught

18VL712-Static timing Analysis

15ECE313-VLSI Design

15ECE378-VLSI System Design

16VL616-Testing of VLSI Circuits

15VL702-System on Chip

VL613-Design for Test

VL612-Digital Design

15ECE364-Digital IC Design

15ECE202-Digital Circuits and System

15ECE303-Linear Integrated Circuits

16VL614-Functional Verification

CMOS integrated Circuits

Analog IC Design

Soft Computing

Digital Circuits and system lab

Industrial Automation Lab

VLSI Design Lab

Student Guidance

Undergraduate Students

Sl. No. Name of the Student(s) Topic Status – Ongoing/Completed Year of Completion
1 K.Vineetha
K.Manoj kumar
M.Buddhavyas		 Error Detection Technique for A Median Filter Ongoing
2 Murugappan M
Mohammed Sarfaraz
Kondreddy Bruhathi Reddy		 Design and Verilog HDL Implementation of carry Skip Adder using Kogge-Stone Tree logic Ongoing
3 K. V. Rajesh
L.Suneel Kumar
B. Lavanya		 Design and analysis of mulitplier with approximate 15:4 compressor and error recovery modules Completed 2020
4 Akilandeswari.M
M.Logeshni
ChilukuriKrishna Harika		 Design of an algorithmic Wallace multiplier using high 5speed counters Completed 2020
5 G Akhil Reddy
P Vallish Kumar
Rao Surya		 FPGA implementation of light weight hardware architecture for “present” cipher Completed 2019
6 MNS Sai Tejesh
P Srikanth Reddy
Praveen Vikas		 Array based approximate arithmetic computing : A general model and applications to multiplier Completed 2019
7 Sappati Aravind Ashok
Thallam Karthik
Viraati Nikhil Reddy		 Implementation of Approximate booth mltiplier Completed 2018
8 A. Chauhan
Arnav Gupta
Prahlad Nag		 Implementation of FIR Filter and MAC Unit by using Neural Networks in FPGA Completed 2018
9 P Divya Rani
P Sai Bharath Nandan
T Sivakumar		 Implementation of radix 4 Booth multiplier Completed 2017
10 C. Srinivas Chandran
Shankar Narayan
K. Mithun Kumar		 Low power and area efficient carry select adder Completed 2017
11 Datla Phanindra Varma
Degala Venkata Akhil
CH Varun		 FPGA implementation of electronic voting machine Completed 2016

Postgraduate Students

Sl. No. Name of the Student(s) Topic Status – Ongoing/Completed Year of Completion
1 KAJA NAGA VENKATA AKHI A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Data paths Ongoing
2 B Sunandha Implementation of modified Dual-CLCG Method for Pseudorandom bit Generation Completed 2020
3 Manasa Kalyan Low complexity LDPC error correction code for modified Anderson PUF to improve its uniformity Completed 2020
4 A Karthik Kumar High Speed Error-Detection and Correction Architectures for Viterbi Algorithm Implementation Completed 2019
5 Pavan Kumar A Pulse based acyclic asynchornous pipline for combinational logic circuits Completed 2019
6 Anil Kumar Reddy Performance analysis of 8-point FFT using approximate radix -8 booth multipliter Completed 2018
7 S. Sandeep Low power and area efficient error tolerant design for parallel filters Completed 2018
8 R Reshma Security Situational Aware Intelligent Road Traffic monitoring Using UAVs Completed 2016
9 V Sunesh Design and Implementation of Fast Floating Point Multiplier Unit Completed 2015
10 T Aswathi All Digital Phase Locked Loop with Input Clock fail Detector Completed 2015
11 S Padmesh Implementation of Viterbi Coder for Text to Speech Synthesis Completed 2015
12 R Reshma Security Incident Management in Ground Transportation System Using UAVs Completed 2015
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