Back close
Admissions
M-Vinodhini_asst-professor_ece_bengaluru_campus

Dr. M. Vinodhini

Assistant Professor (SG), Electronics and Communication Engineering, School of Engineering, Bengaluru

Qualification: M.Tech.
m_vinodhini@blr.amrita.edu
Orcid Profile
M.vinodhini's Google Scholar Profile
Scopus Author ID
Research Interest: Network on Chip architecture, Coding technique for network on chip router, Coding technique for memories, Low-power Digital VLSI architecture

Bio Publications Professional Appointments Recognitions Courses Taught Student Guidance
Bio

Dr. M. Vinodhini currently serves as Assistant Professor (SG) at the Department of Electronics and Communication Engineering, School of Engineering, Amrita Vishwa Vidyapeetham, Bengaluru.

Education

  • 2021: Ph.D. in Network on Chip
    School of Engineering, Amrita Vishwa Vidyapeetham, Bengaluru.
  • 2010: M.Tech. in VLSI Design
    School of Engineering, Amrita Vishwa Vidyapeetham, Bengaluru.
  • 2000: B.E. in Electronics and Communication Engineering
    Madras University, Tamil Nadu.
Publications

Journal Article

Year : 2023

Error correction and crosstalk avoidance code for Network on Chip Router

Cite this Research Publication : Brahmbhatt, B., Dikshitha, K. M., Abhishek, P., M. Vinodhini, “ Error correction and crosstalk avoidance code for Network on Chip Router”, Journal of Integrated Science and Technology, 11(4), 572.

Year : 2021

Crosstalk aware transient error correction coding technique for NoC links

Cite this Research Publication : M. Vinodhini, N.S. Murty, and T.K. Ramesh, “Crosstalk aware transient error correction coding technique for NoC links,” Microelectronics Reliability, Volume 124, September 2021, Impact Factor:1.589. https://doi.org/10.1016/j.microrel.2021.114296.

Publisher : Microelectronics Reliability

Year : 2020

Transient Error Correction Coding Scheme for Reliable Low Power Data Link Layer in NoC

Cite this Research Publication : M. Vinodhini, N. S. Murty, and Dr. T. K. Ramesh, “Transient Error Correction Coding Scheme for Reliable Low Power Data Link Layer in NoC”, IEEE Access, vol. 8, pp. 174614-174628, 2020.

Publisher : IEEE Access, IEEE Institute of Electrical and Electronics Engineers

Year : 2018

Route-on-fly network-on-chip router design with soft-error tolerance

Cite this Research Publication : Sandeep, D., Vinodhini, M., Murty, N.S., “Route-on-fly network-on-chip router design with soft-error tolerance”, Journal of Computational and Theoretical Nanoscience, 2020, 17(1), pp. 329–333.

Publisher : International Conference on Intelligent Computing (ICIC) 2018

Year : 2018

Reliable Low Power NoC Interconnect

Cite this Research Publication : M. Vinodhini and Dr. N.S. Murty, “Reliable low power NoC interconnect”, Microprocessors and Microsystems, vol. 57, pp. 15-22, 2018.

Publisher : Microprocessors and Microsystems

Year : 2012

Interoperability between Wireless Networks Using FPGA Based Advanced Gateway

Cite this Research Publication : M. K.M. and M., V., “Interoperability between Wireless Networks Using FPGA Based Advanced Gateway”, International Forum of Researchers Students and Academician’s (IFRSA’s), International Journal of Mobile and Adhoc Network (IJMAN), vol. 2, no. 2, pp. 240-244, 2012.

Publisher : IJMAN

Year : 2012

Implementation of Blake and RSA in a Fast Authentication Protocol for Wireless Mesh Networks on FPGA

Cite this Research Publication : V. M and Nair, Lpriya, “Implementation of Blake and RSA in a Fast Authentication Protocol for Wireless Mesh Networks on FPGA ”, International Forum of Researchers Students and Academician’s (IFRSA’s), International Journal of Mobile and Adhoc Network (IJMAN), vol. 2, no. 2, pp. 224-228, 2012.

Publisher : IJMAN

Conference Paper

Year : 2023

Low power NoC buffer protection using error correction code

Cite this Research Publication : T. Katheresh I. and M. Vinodhini,” Low Power NoC Buffer Protection using Error Correction Code ”, AIP Conference Proceedings. , 2023, 2725, 040005

Year : 2023

Nibble Based Two Bit Invert Coding Technique for Serial Network on Chip Links

Cite this Research Publication : Anirudh, M.S.S.V.N.K.R.R. , Vatsa, N.R.S. , Vivek, P.V.S. , Vinodhini, M. ,” Nibble Based Two Bit Invert Coding Technique for Serial Network on Chip Links”, 2023 5th International Conference on Electrical, Computer and Communication Technologies, ICECCT 2023 , 2023.

Publisher : IEEE

Year : 2022

High Performance Accurate Multiplier using Hybrid Reverse Carry Propagate Adder

Cite this Research Publication : Bhavani, N.S.V.S.G. , Vinodhini, M. ,” High Performance Accurate Multiplier using Hybrid Reverse Carry Propagate Adder”, 6th International Conference on Electronics, Communication and Aerospace Technology, ICECA 2022 - Proceedings , 2022, pp. 20–25.

Publisher : IEEE

Year : 2021

Regional Congestion Aware Odd even Routing with Fair Arbitration for Network on Chip

Cite this Research Publication : Somisetty, R. , Karthik, V.S.S. , Srujan, M.R.S. , M. Vinodhini,” Regional Congestion Aware Odd even Routing with Fair Arbitration for Network on Chip ”, 4th International Conference on Electrical, Computer and Communication Technologies, ICECCT 2021

Publisher : IEEE

Year : 2021

Transition Based Odd/Full Invert Coding Scheme for Crosstalk Avoidance and Low Power Consumption in NoC Links

Cite this Research Publication : M. Vinodhini and Murty, N. S., “Transition Based Odd/Full Invert Coding Scheme for Crosstalk Avoidance and Low Power Consumption in NoC Links”, in Advances in Signal and Data Processing, Part of the Lecture Notes in Electrical Engineering book series (LNEE,volume 703, Pp. 279 – 298), S. N. Merchant, Warhade, K., and Adhikari, D., Eds. Singapore: Springer Singapore, 2021.

Publisher : Advances in Signal and Data Processing, Springer Singapore, Singapore (2021)

Year : 2021

H-Matrix Based Error Correction Codes for Memory Applications

Cite this Research Publication : C. Bhargavi, Nishanth, D. V. R., Nikhita, P., and M. Vinodhini, “H-Matrix Based Error Correction Codes for Memory Applications”, International Conference on Advances in Electrical, Computing, Communications and Sustainable Technologies (ICAECT 2021). Department of Electrical and Electronics Engineering, Shri Shankaracharya Group of Institutions, SSTC, Bhilai, Chhattisgarh, India, 2021.

Publisher : International Conference on Advances in Electrical, Computing, Communications and Sustainable Technologies (ICAECT 2021).

Year : 2020

Matrix based Error Detection and Correction using Minimal Parity Bits for Memories

Cite this Research Publication : K. Nandan Kumar, Reddy, N. V. S. Anvesh, Shanmukh, P., and M. Vinodhini, “Matrix based Error Detection and Correction using Minimal Parity Bits for Memories”, in 2020 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), Udupi, India, 2020.

Publisher : 2020 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)

Year : 2020

Improved High Speed Approximate Multiplier

Cite this Research Publication : T. Roshini, Krishna, R. S., Reddy, P. K., and M. Vinodhini, “Improved High Speed Approximate Multiplier”, in 2020 4th International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech), Kolkata, India, 2020.

Publisher : 2020 4th International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech)

Year : 2020

Performance Analysis of Different Reduced Precision Redundancy based Full Adders

Cite this Research Publication : S. Krishna and M. Vinodhini, “Performance Analysis of Different Reduced Precision Redundancy based Full Adders”, in 2020 IEEE International Conference for Innovation in Technology (INOCON), Nagarjuna College of Engineering and Technology, Bangalore, 2020

Publisher : Nagarjuna College of Engineering and Technology, Bangalore

Year : 2020

Nibble Based even Invert Code for Serial NoC Links

Cite this Research Publication : S. .S.Varma, N. Vineela, S., G. Sree, N., and M. Vinodhini, “Nibble Based even Invert Code for Serial NoC Links”, in 4th International Conference on Electronics, Communication and Aerospace Technology (ICECA 2020), RVS Technical Campus at Hotel Arcadia, Coimbatore, Tamil Nadu, India, 2020.

Publisher : RVS Technical Campus at Hotel Arcadia, Coimbatore

Year : 2020

Diagonal Hamming Based Multi-Bit Error Detection and Correction Technique for Memories

Cite this Research Publication : M. G. Sai, K. Avinash, M., L. Naidu, S. Ganesh, M. Rohith, S., and M. Vinodhini, “Diagonal Hamming Based Multi-Bit Error Detection and Correction Technique for Memories”, in 9th International Conference on Communication and Signal Processing - ICCSP 2020, Adhiparasakthi Engineering College, Melmaruvathur, India , 2020.

Publisher : Adhiparasakthi Engineering College

Year : 2020

Code with Crosstalk Avoidance and Error Correction for Network on Chip Interconnects

Cite this Research Publication : K. Anupama Sa Lakshmi, M, K. A. ., Sri, K. Madhu, and M. Vinodhini, “Code with Crosstalk Avoidance and Error Correction for Network on Chip Interconnects”, in 4th International Conference on Trends in Electronics and Informatics (ICOEI 2020) , SCAD College of Engineering and Technology, Tirunelveli, India, 2020

Publisher : SCAD College of Engineering and Technology, Tirunelveli

Year : 2019

Logic Encryption of Combinational Circuits

Cite this Research Publication : K. Pritika and M. Vinodhini, “Logic Encryption of Combinational Circuits”, in 2019 3rd International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech), Kolkata, India, 2019.

Publisher : 2019 3rd International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech)

Year : 2019

Fast Error Correction for Header Flit in NoC

Cite this Research Publication : T. Sai Srinat V. Reddy, G. Reddy, H. Sekhar, K. Reddy, J., and M. Vinodhini, “Fast Error Correction for Header Flit in NoC”, in 2019 International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, 2019.

Publisher : 2019 International Conference on Communication and Electronics Systems (ICCES)

Year : 2019

Efficient Multi-Bit Error Tolerant design for MVM

Cite this Research Publication : P. G. Hitesh, Venkatesh, P., P Reddy, S. Thirumal, and M. Vinodhini, “Efficient Multi-Bit Error Tolerant design for MVM”, in 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA), Coimbatore, India, 2019.

Publisher : 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA)

Year : 2019

Weight Based Segmentation of Scan Cells for Efficient ATPG Technique

Cite this Research Publication : P. Aswathy, M. Vinodhini, and Vipin, K., “Weight Based Segmentation of Scan Cells for Efficient ATPG Technique”, in 2019 3rd International Conference on Computing Methodologies and Communication (ICCMC), Erode, India, 2019.

Publisher : 2019 3rd International Conference on Computing Methodologies and Communication (ICCMC)

Year : 2019

2D Mapping Robot using Ultrasonic Sensor and Processing IDE

Cite this Research Publication : R. H., Adithi, R., M. Vinodhini, and Jayasree M. Oli, “2D Mapping Robot using Ultrasonic Sensor and Processing IDE”, 2019 International Conference on Vision Towards Emerging Trends in Communication and Networking (ViTECoN), 2019.

Publisher : 2019 International Conference on Vision Towards Emerging Trends in Communication and Networking (ViTECoN)

Year : 2019

Multi-bit error correction coding with crosstalk avoidance using parity sharing technique for NoC

Cite this Research Publication : S. Rajagopal, M. Vinodhini, and Murty, N. S., “Multi-bit error correction coding with crosstalk avoidance using parity sharing technique for NoC”, in Proceedings - 2018 IEEE 4th International Symposium on Smart Electronic Systems, iSES 2018, 2019, pp. 249-254.

Publisher : Proceedings - 2018 IEEE 4th International Symposium on Smart Electronic Systems, iSES 2018

Year : 2018

Improving the Reliability of Embedded Memories using ECC and Built-In Self-Repair Techniques

Cite this Research Publication : R. Manasa, Ganapathi Hegde, and M. Vinodhini, “Improving the Reliability of Embedded Memories using ECC and Built-In Self-Repair Techniques”, in 2018 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT), Msyuru, India, 2018.

Publisher : 2018 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques

Year : 2018

Multi-Bit Low Redundancy Error control with Parity Sharing for NoC Interconnects

Publisher : International Conference on Communication and Electronics Systems (ICCES) 2018

Year : 2018

Joint Crosstalk Avoidance with Multiple Bit Error Correction Coding Technique for NoC Interconnect

Publisher : 7th IEEE International conference on Advances in Computing, Communications and Informatics (ICACCI)

Year : 2017

A Unique Low Power Network-an-Chip Virtual Channel Router

Cite this Research Publication : O. L. M. Srrayvinya, M. Vinodhini, and Dr. N.S. Murty, “A Unique Low Power Network-an-Chip Virtual Channel Router”, in 2017 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2017, 2017.

Publisher : 2017 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2017

Year : 2017

Merged arbitration and switching techniques for network on chip router

Cite this Research Publication : M. Vinodhini and Dr. N.S. Murty, “Merged arbitration and switching techniques for network on chip router”, in 2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS), 2017.

Publisher : 2017 International conference on Microelectronic Devices, Circuits and Systems

Year : 2017

Horizontal-vertical parity and diagonal hamming based soft error detection and correction for memories

Cite this Research Publication : P. Raha, M. Vinodhini, and Dr. N.S. Murty, “Horizontal-vertical parity and diagonal hamming based soft error detection and correction for memories”, in 2017 International Conference on Computer Communication and Informatics (ICCCI), 2017.

Publisher : 2017 International Conference on Computer Communication and Informatics

Year : 2017

Error detection and correction in semiconductor memories using 3D parity check code with hamming code

Cite this Research Publication : S. Tambatkar, Menon, S. N., Sudarshan, V., M. Vinodhini, and Dr. N.S. Murty, “Error detection and correction in semiconductor memories using 3D parity check code with hamming code”, in 2017 International Conference on Communication and Signal Processing (ICCSP), 2017.

Publisher : 2017 International Conference on Communication and Signal Processing

Year : 2017

Data Flipping Coding Technique to Reduce NOC Link Power

Cite this Research Publication : M. Moulika, M. Vinodhini, and Dr. N.S. Murty, “Data Flipping Coding Technique to Reduce NOC Link Power”, in 2017 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2017, Coimbatore, India, 2017.

Publisher : 2017 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2017

Year : 2015

Reliable Router Architecture with Elastic Buffer for NoC Architecture

Cite this Research Publication : R. Louis, Vinodhini, M., and Dr. N.S. Murty, “Reliable router architecture with elastic buffer for NoC architecture”, in 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, 2015.

Publisher : 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015

Year : 2015

Merged switch allocation and transversal with dual layer adaptive error control for Network-on-Chip switches

Cite this Research Publication : Ha Kalwad, Neeharika, Sb, Divya, Sc, M. Vinodhini, and Dr. N.S. Murty, “Merged switch allocation and transversal with dual layer adaptive error control for Network-on-Chip switches”, in 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, 2015.

Publisher : 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015

Year : 2015

A fault tolerant NoC architecture with runtime adaptive double layer error control and crosstalk avoidance

Cite this Research Publication : M. Vinodhini, Lillygrace, K., and Dr. N.S. Murty, “A fault tolerant NoC architecture with runtime adaptive double layer error control and crosstalk avoidance”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015, 2015.

Publisher : 2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015

Book Chapter

Year : 2021

Hamming Based Multiple Transient Error Correction Code for NoC Interconnect

Cite this Research Publication : M. Vinodhini and Dr. N.S. Murty, “Hamming Based Multiple Transient Error Correction Code for NoC Interconnect”, ”, in Lecture Notes in Electrical Engineering, Vol. 711, PP. 569 – 579, 2021

Publisher : Lecture Notes in Electrical Engineering, Vol. 711, PP. 569 – 579, 2021

Professional Appointments
  • July 2006 – Present: School of Engineering, Amrita Vishwa Vidyapeetham, Bengaluru, Karnataka.
  • April 2001 – July 2004: Bannari Amman Institute of Technology, Sathyamangalam, Tamil Nadu.

Membership in Professional Bodies

  • IEEE-CAS
Recognitions

Certificates, Awards & Recognitions

  • Ms. Vinodhini M. as Inventor and Dr. N. S. Murty as Co-Inventor, a Patent titled, “System and Methods of an Efficient and High Throughput Network-on-Chip Architecture” is granted on 13th November 2023
  • Received the AMRITA PUBLICATION MERIT AWARD in 2021.
  • As part of “National Mission Project on Education through ICT – Developing suitable pedagogical methods for various classes, intellectual calibers and research in e-learning- Main Phase”, sponsored by MHRD, Government of India, the development of course titled “Telecom Transmission and Switching” has been successfully completed and has been released to IIT Kharagpur by Dr. Dhanesh G Kurup (Principal Developer), Ms. M. Vinodhini (CoDeveloper) and Ms. R. V. Sanjika Devi (CoDeveloper) in March 2016. Duration:4years.Amount:700000
Courses Taught
  • Data communication and networks
  • Principles of VLSI Testing
  • Data acquisition and communication
  • Electronics engineering
  • Digital Telephony
  • Digital IC design
  • Microprocessors
  • Wireless communication
  • Cellular and mobile communication
  • Analog Communication
  • Network on Chip
  • Design for Test and Testing
  • Physical design for ICs
  • Digital Circuits and Systems
Student Guidance

Research Scholars Details

1. Anjana Ramachandran(Full time research scholar. Amrita School of Engineering, Bangalore)
2. Abhishek Tiwari (CDAC)

Undergraduate Students

Sl. No. Name of the Student(s) Topic Status – Ongoing/Completed Year of Completion
1 Visheshwar Rao, K. S. Nakul, M. Krishna Chaitanya Reddy Design of an Optimized Product Code for Space Application Ongoing 2024
2 Sanisetty Venkata Kartheek, Srinadhu Sai Sagar, Tulasi Venkata Sudeep High Performance Multiply Accumulate Unit for Embedded System Ongoing 2024
3 Patthi Harish, Paturi Abhiram, V.Praveen Kumar CRC-based Correction of Multiple Errors using an Optimized Lookup Table Ongoing 2024
4 M.Mounika Implementation of Spanning tree protocol Completed 2023
5 Bellala Navyasri, Sankurathri Shreyaswi, Veerendra Sai Manasali High-Speed Congestion Aware Routing Algorithm for Network on Chip Architecture Completed 2023
6 M.Saahithya, N.Hemanth Optimization of a Leading Zero Count structure for Arithmetic Computations Completed 2023
7 J. Shivani, M.Shankar Teja Reddy, N.Neeraj Implementation of Correction Masking Techniques for Error correction decoders Completed 2023
8  Pandavula Abhishek,

Kmdikshitha,

Brinda Hitendraprasad

  Joint Crosstalk Avoidance and Error Control Coding Technique for Network on Chip Links Completed 2022
9 M.S.S.V.N.K.R.R.Anirudh,

N.Rajeev Sri Vatsa,

P.V. Sai Vivek

  Efficient Coding Technique for the Crosstalk Minimization in Network on Chips Completed 2022
10  Meda Rama Sai Srujan

Rohith Somisetty

V. S. S. Karthik

  Congestion Aware Fair Arbitration routing algorithm for Network on Chip Completed 2021
11 Kuber Kandula

L. Sri Ganesh naidu

Netheti Priyanka

  Efficient Crosstalk Avoidance Coding technique For Network On Chip Completed 2021
12 Konda Nandan Kumar, NVS Anvesh Reddy, Peela Shanmukh Matrix based Error Detection and Correction using

Minimal Parity Bits for Memories

 Completed 2020
13 Chukkapalli Bhargavi,

V R Nishanth,

Peddi Nikhita

 H-Matrix Based Error Correction Codes for

Memory Applications

 Completed 2020
14 Sruthi.S.Varma, N. Sai Vineela, G. Navya Sree Nibble Based Even Invert Code for Serial NoC

Links

 Completed 2020
15 T.Roshini, R.Sai Krishna, P.Kaushik Reddy Improved High Speed Approximate Multiplier Completed 2020
16 V.Taraka Sai Srinatha Reddy, G.Hema Sekhar Reddy, K.Jeshmitha Reddy Fast Error Correction for Header Flit in NoC Completed 2019
17 P G Hitesh, Pasam Venkatesh, P Sai Thirumal Reddy Efficient Multi-Bit Error Tolerant design for MVM Completed 2019
18 T Siva Teja, T Sai Kiran, T.V.V Satya Narayana Joint Crosstalk Avoidance with Multiple Bit Error

Correction Coding Technique for NoC

Interconnect

 Completed 2018
19 Paluru Venkata Koushik Sai

Lingala Ramsaran Reddy

  Low Power Router Design For Noc Completed 2017
20 Soma Sri Sai Harsha

Srinandan Moturi

Srivaths Kumar

 Arbiter and Crossbar switch design in Low power router architecture for Network on Chip Completed 2017
21 Shivani Tambatkar

Siddharth Narayan Menon

Sudarshan V

 3-Dimensional Parity Check Code With Hamming Code For Error Detection And Correction Completed 2016
22 T Prudhvi Raj

N Pruthivi Muhilan

Saran Rishi

 Power Efficient Network On Chip Architecture
With And Without FIFO Buffers		 Completed 2015
23 Aparna S Kamath

Avani P

Divya R

 Efficient Integrated Arbitration And Switching For Network On Chip Completed 2015
24 Havisha Kalwad, Sompalli Neeharika, Songa Divya Merged Switch Allocation and Transversal with Dual Layer Adaptive Error Control for Network-on-Chip Switches Completed 2014

Postgraduate Students

Sl. No. Name of the Student(s) Topic Status – Ongoing/Completed Year of Completion
1 Shashank Gupta Design and implementation of a Low-Power Linear Feedback Shift Register using Clock Gating Technique Ongoing 2024
2 Sirisha Mallaiah Design and implementation of an efficient soft error resilient SRAM based TCAM completed 2023
3  Lakshmi Nair An Enhanced Low-Power Coding Technique for Serial NoC Links completed 2022
4  N.S.V.S.G. Bhavani  Delay and Area Efficient Approximate Multiplier using Reverse Carry Propagate Full Adder completed 2022
5 Thanga Katheresh I Efficient NoC Buffer Protection using Error Correction Code Completed 2021
6 P. Sai Krishna Performance Analysis of Different Reduced

Precision Redundancy based Full Adders

 Completed 2020
7 P Aswathy Weight Based Segmentation Of Scan Cells For

Efficient Atpg Technique

 Completed 2019
8 Pritika K Logic Encryption Of Combinational Circuits Completed 2019
9 Darshanala Sandeep Soft-Error Toerant Network-On-Chip Router Completed 2018
10 Supriya Rajagopal Multi-Bit Error Correction Coding With Crosstalk

Avoidance Using Parity Sharing Technique For NOC

 Completed 2018
11  U. Sai Himaja  Multi  Bit Low Redundancy Error

Control With

Parity Sharing For No

C Interconnects

 Completed 2018
12  M.Moulika Data flipping coding technique to reduce NoC Link Power

 

 Completed 2017
13 O L M.Srrayvinya A Unique Low Power Network-on-Chip Virtual

Channel Router

 Completed 2017
14 Paromita Raha Horizontal-Vertical Parity and Diagonal Hamming

Based Soft Error Detection and Correction for

Memories

 Completed 2016
15 Lillygrace K A Fault Tolerant NoC Architecture with runtime

adaptive double layer error control and crosstalk

avoidance

 Completed 2015
16 Roshna Louis Reliable Router Architecture with Elastic Buffer for NoC

Architecture

 Completed 2014

Research Scholars

Sl. No. Name of the Student(s) Topic Status – Ongoing/Completed Year of Completion
1 Abhishek Tiwari AI Hardware Accelerator Ongoing 2026
2 Anjana Ramachandran Network on Chip Router Ongoing 2025
Admissions Apply Now