Back close
Admissions

Navya Mohan

Assistant Professor (SG), Electronics and Communication Engineering, School of Engineering, Coimbatore

Qualification: M.Tech.
m_navya@cb.amrita.edu
Ph: +91 422 2685000 Ext. 5726
Navya Mohan's Google Scholar Profile
Research Interest: Digital Design, Signals & Systems, Very-Large-Scale Integration (VLSI) Testing

Bio Publications Education Professional Experience Academic Responsibilities Undergraduate Courses Handled Post-Graduate / PhD Courses Handled Participation in Faculty Development / STTP / Workshops /Conferences Academic Research – PG Projects Developmental Activities
Bio

Navya Mohan is working as an Assistant Professor (SG) in ECE Department at Amrita Vishwa Vidyapeetham, Coimbatore. She completed her M.Tech in VLSI Design from Amrita Vishwa Vidyapeetham in 2013 and B.Tech in Electronics and Communication Engineering from College of Engineering, Adoor in 2010. Her area of interests includes Low power VLSI Testing and Reconfigurable Computing. She is also GATE qualified.

 

Publications

Journal Article

Year : 2016

A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults

Cite this Research Publication : N. Mohan and Dr. Anita J. P., “A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults”, International Journal of Mathematical Modelling and Numerical Optimisation, vol. 7, pp. 83-96, 2016.

Publisher : Inderscience Enterprises Ltd.

Year : 2014

N-Detect Test Pattern Generation And Relaxation Using ZDD

Cite this Research Publication : B. D. Kumar Reddy and Mohan, N., “N-Detect Test Pattern Generation And Relaxation Using ZDD”, International Journal of Electrical, Electronics and Data Communication, vol. 2, no. 7, p. Online-Ressource, 2014.

Publisher : International Journal of Electrical, Electronics and Data Communication

Conference Paper

Year : 2018

Instantaneous Feedback Pedometer With Emergency Gps Tracker

Cite this Research Publication : M. B. Nair, Kumar, S. R., Kishore, N. A., Mohan, N., and Anudev J., “Instantaneous Feedback Pedometer With Emergency Gps Tracker”, in 2nd International Conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC)I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC), Palladam, India, 2018.

Publisher : 2nd International Conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC)

Year : 2017

Efficient Test Scheduling for Reusable BIST in 3D stacked ICs

Cite this Research Publication : N. Mohan, Krishnan, M., S. Rai, K., Mathu, M. M., and Sivakalyan, S., “Efficient Test Scheduling for Reusable BIST in 3D stacked ICs”, in 2017 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2017, 2017, vol. 2017-January, pp. 1349-1355.

Publisher : Institute of Electrical and Electronics Engineers Inc.,

Conference Proceedings

Year : 2019

Improved Test Coverage by Observation Point Insertion for Fault Coverage Analysis

Cite this Research Publication : V. Veena, Prabhu E., and Mohan, N., “Improved Test Coverage by Observation Point Insertion for Fault Coverage Analysis”, 2019 3rd International Conference on Trends in Electronics and Informatics (ICOEI). 2019.

Publisher : ICOEI

Education
  • Pursuing: Ph. D. in VLSI Testing
    Amrita Vishwa Vidyapeetham
  • 2013: M. Tech. in VLSI Design
    Amrita Vishwa Vidyapeetham
Professional Experience
Year Affiliation
2013 – Till Present Assistant Professor, Amrita Vishwa Vidyapeetham
Domain : Teaching and Research
Academic Responsibilities
SNo Position Class / Batch
1. Class Adviser 2016 – 20
Undergraduate Courses Handled
  1. VLSI Design
  2. Electronics Circuits
  3. Linear Integrated Circuits
  4. Digital Circuits and Systems
  5. Microcontroller and its Applications
  6. Computer System Architecture
Post-Graduate / PhD Courses Handled
  1. Introduction to Computer Architecture (Automotive Electronics)
Participation in Faculty Development / STTP / Workshops /Conferences
SNo Title Organization Period Outcome
1. ISTE Workshop on Signals and Systems IIT Kharagpur 2 – 12 January 2014 Teaching learning process
Academic Research – PG Projects
SNo Name of the Scholar Programme Specialization Duration Status
1. Veena V. VLSI Design Low Power VLSI Testing 2018-19 Ongoing
2. Anthony Thomas VLSI Design Low Power VLSI Testing 2018-19 Ongoing
Developmental Activities
SNo Name & Description Outcome
1. Instruction material for ECE100 Electronics Engineering Course for 2014 Curriculum Uniform course delivery throughout all the branches of Engineering.
Admissions Apply Now