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Geethu-R-S_asst-professor_ece_engineering_amritauniversity_amritapuri

Geethu R. S.

Assistant Professor(Sr. Gr.), Department of Electronics and Communication Engineering, School of Engineering, Amritapuri

Qualification: BE, M.Tech.
geethurs@am.amrita.edu
Google Scholar Profile
Scopus Author ID
Research Interest: Digital Circuits & Systems, Secured Testing, Security of Logic Circuits, Testing of VLSI Circuits
Date of Joining: 22/12/2004
Nature of Association: Regular

Bio Publications FDP / Workshops Attended Invited Talks Membership Conferences Organized Fellowships Received Certifications Other Recognitions Workshops/ Trainings/ Attended
Bio

Geethu R. S. currently serves as an Assistant Professor (Sr. Gr.) at the Department of Electronics and Communication Engineering at Amrita School of Engineering, Amritapuri. She has completed M. Tech. in Microelectronics and VLSI from National Institute of Technology Calicut. Currently pursuing Ph. D. Research in Amrita Vishwa Vidyapeetham.

Research/ Project going on in the area of DFT/ Testability

Digital VLSI Testing, Design of Digital Systems and Circuits in HDL, Verification and synthesis, FPGA implementations

Experience (Teaching)

18 years

Education

  • Currently pursuing Ph. D. Research in Amrita Vishwa Vidyapeetham.
  • M. Tech. (Microelectronics & VLSI) –National Institute of Technology, Calicut-2012
  • B. E. (Electronics & Communication Engineering) – Manonmaniam Sundaranar University-2003
Publications

Journal Article

Year : 2017

Extension of Blind Source Separation Model for Near Field Ground Borne Vibrations

Cite this Research Publication : R.S. Geethu, V, P. K., and M, K. Kumar, “Extension of Blind Source Separation Model for Near Field Ground Borne Vibrations”, KSEBEA Hydel, vol. 63, no. 23-28, 2017.

Publisher : KSEBEA Hydel,

Year : 2016

New Method for Source Separation of Ground Borne Vibration Signals

Cite this Research Publication : P. K. V, M., K. Kumar, and R.S. Geethu, “New Method for Source Separation of Ground Borne Vibration Signals”, Hydel Journal, vol. 62, pp. 48-54, 2016.

Publisher : Hydel Journal

Year : 2015

Source Separation of Heartbeat Sounds for Effective E-Auscultation

Cite this Research Publication : R.S. Geethu, Krishnakumar, M., Pramod, K. V., and George, S. N., “Source Separation of Heartbeat Sounds for Effective E-Auscultation”, Journal of The Institution of Engineers (India), 2015.

Publisher : Journal of The Institution of Engineers

Year : 2014

A scheme for improving the effectiveness of Auscultation

Cite this Research Publication : K. M, K.V, P., and R.S. Geethu, “A scheme for improving the effectiveness of Auscultation”, Journal of Science, Technology and management, vol. 07, 2014.

Publisher : Journal of Science, Technology and management

Year : 2011

Source Separation of Heartbeat Sounds

Cite this Research Publication : M. Krishnakumar, Pramod, K. V., and R.S. Geethu, “Source Separation of Heartbeat Sounds”, MES JTM, vol. 1, 2 vol., no. 65-71, 2011.

Publisher : MES JTM

Year : 2011

A Low Cost Scheme for Tracking the Lives Buried in Landslides

Cite this Research Publication : M. Krishnakumar, Pramod, K. V., and R.S. Geethu, “A Low Cost Scheme for Tracking the Lives Buried in Landslides”, IJCA Special Issue on “Computational Science - New Dimensions & Perspectives”, 2011.


Publisher : IJCA Special Issue on “Computational Science

Conference Paper

Year : 2022

Design of a Programmable Low Power Linear Feedback Shift Register for BIST Applications

Cite this Research Publication : M. B, G. Remadevi and R. Bakthavatchalu, "Design of a Programmable Low Power Linear Feedback Shift Register for BIST Applications," 2022 IEEE International Test Conference India (ITC India), 2022, pp. 1-4, doi: 10.1109/ITCIndia202255192.2022.9854556

Publisher : IEEE

Year : 2022

Design and Analysis of Multi-Bit Linear Feedback Shift Register based PRNG with FPGA Implementation using different Primitive Polynomials

Cite this Research Publication : S. Sony, A. P. V and G. R.S., "Design and Analysis of Multi-Bit Linear Feedback Shift Register based PRNG with FPGA Implementation using different Primitive Polynomials," 2022 2nd International Conference on Intelligent Technologies (CONIT), 2022, pp. 1-7, doi: 10.1109/CONIT55038.2022.9848174

Publisher : IEEE

Year : 2022

Reconfigurable Linear Feedback Shift Register

Cite this Research Publication : Madhulatha Kamma , Jyothika Karasani , Somanathan, Geethu Remadevi , Bhakthavathchalu, Ramesh ,"Reconfigurable Linear Feedback Shift Register",https://www.scopus.com/record/display.uri?eid=2-s2.0-85127327122&origin=resultslist&sort=plf-f

Publisher : Elsevier

Year : 2022

Reconfigurable and Parameterizable Pseudorandom Pattern Generators for Built-in Self Test

Cite this Research Publication : Madhulatha, Kamma, Jyothika, Karasani,Harini, Sirikonda Venkata Bala, Somanathan, Geethu Remadevi, Bhakthavathchalu, Ramesh ," Reconfigurable and Parameterizable Pseudorandom Pattern Generators for Built-in Self Test",7th International Conference on Communication and Electronics Systems, ICCES 2022 - Proceedings

Publisher : Elsevier

Year : 2022

A Proposal for Programmable Pattern Generator and its FPGA implementation

Cite this Research Publication : Bhakthavatchalu Ramesh, Somanathan Geethu Remadevi,"A Proposal for Programmable Pattern Generator and its FPGA implementation", 3rd IEEE International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI SATA 2022

Publisher : Elsevier

Year : 2022

A Proposal for Low Power Test Pattern Generator

Cite this Research Publication : Maddala Vamsi Krishna, Duppala Tagore, Mani Srikara Yaswanth Nandigam, Palla Narasimha, Udayagiri Rahul and Geethu R. S., "A Proposal for Low Power Test Pattern Generator," 2022 4th International Conference on Smart Systems and Inventive Technology (ICSSIT), 2022, pp. 648-653, doi: 10.1109/ICSSIT53264.2022.9716394.

Publisher : IEEE

Year : 2022

A Programmable and Parameterisable Reseeding Linear Feedback Shift Register

Cite this Research Publication : Hudhaifah Ibn Saleem; Geethu R. S. and Ramesh Bhakthavatchalu, "A Programmable and Parameterisable Reseeding Linear Feedback Shift Register," 2022 Second International Conference on Artificial Intelligence and Smart Energy (ICAIS), 2022, pp. 1629-1633, doi: 10.1109/ICAIS53314.2022.9742870.

Publisher : IEEE

Year : 2022

A Proposal for Design and Implementation of a Low Power Test Pattern Generator for BIST Applications

Cite this Research Publication : Malini Mukherjee, Geethu R S and Ramesh Bhakthavatchalu, "A Proposal for Design and Implementation of a Low Power Test Pattern Generator for BIST Applications," 2022 Second International Conference on Artificial Intelligence and Smart Energy (ICAIS), 2022, pp. 1520-1524, doi: 10.1109/ICAIS53314.2022.9742920.

Publisher : IEEE

Year : 2022

Design and Implementation of Programmable Multiple Input Signature Register

Cite this Research Publication : Ashutosh Agnihotri; Geethu Remadevi Somanathan; Ramesh Bhakthavatchalu, "Design and Implementation of Programmable Multiple Input Signature Register," 2022 Second International Conference on Artificial Intelligence and Smart Energy (ICAIS), 2022, pp. 1536-1540, doi: 10.1109/ICAIS53314.2022.9742968.

Publisher : IEEE

Year : 2022

Programmable Variable-Length Pseudo-Random Sequence Generator

Cite this Research Publication : Doriginti Mohammad, Kanna Rakesh, Geethu Remadevi Somanathan and Ramesh Bhakthavatchalu, "Programmable Variable-Length Pseudo-Random Sequence Generator," 2022 Second International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT), 2022, pp. 1-4, doi: 10.1109/ICAECT54875.2022.9808067.

Year : 2021

Analysis of a Novel Reseeding Pattern Generator

Cite this Research Publication : Vikranth, Chinnapapakkagari Sreenivasa, Mohammad, Doriginti, Somanathan, Geethu Remadevi, Bhakthavatchalu, Ramesh," Analysis of a Novel Reseeding Pattern Generator",Proceedings - 2nd International Conference on Smart Electronics and Communication, ICOSEC 2021
,

Publisher : Elsevier

Year : 2021

Design and Analysis of Test Pattern Generator by combining internal and external LFSR

Cite this Research Publication : Vikranth, Chinnapapakkagari Sreenivasa, Rakesh, Kanna, Jagadeesh, Bodavula, Mohammad, Doriginti, Somanathan, Geethu Remadevi, Bhakthavatchalu, Ramesh, "Design and Analysis of Test Pattern Generator by combining internal and external LFSR", Proceedings of the 5th International Conference on Trends in Electronics and Informatics, ICOEI 2021.

Publisher : Elsevier

Year : 2021

Design and analysis of gray code generator as test pattern generator

Cite this Research Publication : Narasimha, Palla, Krishna, Maddala Vamsi , Somanathan, Geethu Remadevi,Bhakthavatchalu, Ramesh," Design and analysis of gray code generator as test pattern generator", Proceedings of the 6th International Conference on Communication and Electronics Systems, ICCES 2021

Publisher : Elsevier

Year : 2021

Logic Obfuscation Technique for Securing Test Pattern Generators

Cite this Research Publication : Bhakthavatchalu Ramesh ,Sumanth, B. Naga, Naidu P. Shanmukha Naga, Koduri, Pavan Sri Ram, v, Somanathan, Geethu Remadevi,"Logic Obfuscation Technique for Securing Test Pattern Generators",https://www.scopus.com/record/display.uri?eid=2-s2.0-85116708198&origin=resultslist&sort=plf-f

Publisher : Elsevier

Year : 2021

Balanced Scan Chain Analysis to Improve Fault Coverage in VLSI circuits

Cite this Research Publication : R.S. Geethu, Bhakthavathchalu, R., and Krishnakumar, M., “Balanced Scan Chain Analysis to Improve Fault Coverage in VLSI circuits”, in 2021 6th International Conference on Inventive Computation Technologies (ICICT), Coimbatore, India, 2021.

Publisher : 2021 6th International Conference on Inventive Computation Technologies (ICICT),

Year : 2021

Secured Test Pattern Generators for BIST

Cite this Research Publication : S. Naga Naidu P., B., N. Sumanth, Pavan, S. Ram Koduri, M., S. Ram Teja, R.S. Geethu, and Bhakthavatchalu, R., “Secured Test Pattern Generators for BIST”, in 2021 5th International Conference on Computing Methodologies and Communication (ICCMC), Erode, India, 2021.

Publisher : 2021 5th International Conference on Computing Methodologies and Communication (ICCMC)

Year : 2020

Synthesis of Synchronous Gray Code Counters by Combining Mentor Graphics HDL Designer and Xilinx VIVADO FPGA Flow

Cite this Research Publication : S. Satya Sri Seeram, Polireddi, S. Naga Naidu, R.S. Geethu, and Bhakthavatchalu, R., “Synthesis of Synchronous Gray Code Counters by Combining Mentor Graphics HDL Designer and Xilinx VIVADO FPGA Flow”, in 2020 International Conference on Communication and Signal Processing (ICCSP), Chennai, India, 2020.

Publisher : 2020 International Conference on Communication and Signal Processing (ICCSP),

Year : 2020

A Proposal for Synthesis of Synchronous Counters

Cite this Research Publication : N. B. Sumanth, B. Reddy, L., R.S. Geethu, and , “A Proposal for Synthesis of Synchronous Counters”, in 2020 4th International Conference on Trends in Electronics and Informatics (ICOEI)(48184), Tirunelveli, India, 2020.

Publisher : 2020 4th International Conference on Trends in Electronics and Informatics (ICOEI)(48184),

Year : 2020

Synthesis of Pseudorandom Number Generator by Combining Mentor Graphics HDL Designer and Xilinx Vivado FPGA Flow

Cite this Research Publication : R.S. Geethu, Bhakthavathchalu, R., and Krishnakumar, M., “Synthesis of Pseudorandom Number Generator by Combining Mentor Graphics HDL Designer and Xilinx Vivado FPGA Flow”, in Advances in Communication Systems and Networks, Singapore, 2020.

Publisher : Advances in Communication Systems and Networks,

Year : 2019

Comparative Study of Test Pattern Generation Systems to Reduce Test Application Time

Cite this Research Publication : P. Snehal Dilip, R.S. Geethu, and Bhakthavatchalu, R., “Comparative Study of Test Pattern Generation Systems to Reduce Test Application Time”, in 2019 9th International Symposium on Embedded Computing and System Design (ISED), Kollam, India, 2019.

Publisher : 2019 9th International Symposium on Embedded Computing and System Design (ISED),

Year : 2019

Reseeding LFSR for Test Pattern Generation

Cite this Research Publication : P. Snehal Dilip, R.S. Geethu, and Bhakthavatchalu, R., “Reseeding LFSR for Test Pattern Generation”, in 2019 International Conference on Communication and Signal Processing (ICCSP), Chennai, India, 2019.

Publisher : 2019 International Conference on Communication and Signal Processing (ICCSP),

Year : 2018

Architecture of Parallel CRC Encoder Using State Space Transformations

Cite this Research Publication : L. S. Prabha and R.S. Geethu, “Architecture of Parallel CRC Encoder Using State Space Transformations”, in 2018 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT), Bengaluru, India, 2018.

Publisher : 2018 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT),

Year : 2018

Design for a Programmable Alarm Clock using Alphanumeric Display (PACAD)

Cite this Research Publication : K. Sai Sandilya, Eswari, M., R.S. Geethu, B, B., and , “Design for a Programmable Alarm Clock using Alphanumeric Display (PACAD)”, in 2018 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), Madurai, India, 2018.

Publisher : 2018 IEEE International Conference on Computational Intelligence and Computing Research

Year : 2015

A proposal for source separation of ground borne vibration signals and its FPGA implementation

Cite this Research Publication :
R.S. Geethu, Kumar, MbKrishna, and George, S. Nc, “A proposal for source separation of ground borne vibration signals and its FPGA implementation”, in 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, 2015

Publisher : 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015

Year : 2014

A scheme for source separation of ground borne vibrations

Cite this Research Publication : K. M. Kumar, R.S. Geethu, and Pramod, K. V., “A scheme for source separation of ground borne vibrations”, in International Conference on Communication and Network Technologies, Sivakasi, India, 2014.

Publisher : International Conference on Communication and Network Technologies,

Year : 2014

Source Separation of ground borne low level vibration signals using statistical methods

Cite this Research Publication : K. Kumar M., R.S. Geethu, and V., P. K., “Source Separation of ground borne low level vibration signals using statistical methods”, in International Conference on Advances in Computing, Communication and Information Science (ACCIS-2014), 2014.

Publisher : International Conference on Advances in Computing, Communication and Information Science.

Year : 2012

A Proposal for Source Separation of Heartbeat Sounds and Its FPGA Implementation

Cite this Research Publication : R.S. Geethu, George, S. N., and M. Kumar, K., “A Proposal for Source Separation of Heartbeat Sounds and Its FPGA Implementation”, in 2012 International Conference on Communication Systems and Network Technologies, Rajkot, Gujarat, India, 2012.

Publisher : IEEE

Year : 2010

A Life Tracking System based on Audio Source Separation

Cite this Research Publication : K. Kumar M, V, P. K., and R.S. Geethu, “A Life Tracking System based on Audio Source Separation”, in IETE Zonal seminar on Networking Paradigms and Cyber Security, 2010.

Publisher : IETE Zonal seminar on Networking Paradigms and Cyber Security,

Conference Proceedings

Year : 2020

Gray code for test pattern generation

Cite this Research Publication : P. Dilip, R.S. Geethu, and Bhakthavatchalu, R., “Gray code for test pattern generation”, in AIP Conference Proceedings, 2020.

Publisher : AIP Conference Proceedings

FDP / Workshops Attended
S. No. Name of the International Seminar/Workshop/Conference Date Name of Organizing Institution & Venue
1 LIFE SKILLS: PERSONAL EFFECTIVENESS 2021-06-21 to 2021-06-25 International Institute of HealthManagement Research, Delhi.
2. Emerging Technologies in Healthcare: IOT,AI, Computational Neuroscience, Wearable Technologies” 2021-1-18 to 2021-1-22 AICTE Training And Learning (ATAL) Academy Online FDP
3 3-Day Cadence OnlineTools Training 28-july-2022 to 3-July-2022 ECE Dept. ASE
4 FPGA Design using Vivado Design Suite basic 5th to 7th Jan 2022 Sandeepani School of Embedded System Design, Bangalore
5 Two Day National Open Workshop on “Getting Aligned to thePublishing Process”- Author Workshop, on Friday 25 September, 2020 Elsevier
6. Design, Implementation and Verification in VLSI 27-Apri-2020 to 1-May-2020 Sandeepani School of Embedded System Design, Bangalore.
Invited Talks
  • “How to execute successful B.Tech Projects” organized by IEEE PES Kerala Chapter for B.Tech Students on 20-Sep-2020
Membership
  • Institution of Electronics and Telecommunication Engineers (IETE)
Conferences Organized
S. No. Name of the Seminar / Conference organised Duration Number of Participants Source of Funding Seminar / Conference Outcome
From To
1. 3-Day Cadence OnlineTools Training 28-july-2022 3-July-2022 40 University Introduction for Cadence tools
2 Introduction to Mentor Graphics EDA Tools: Provided by: Trident TechlabsPvt. Ltd 30-Oct-2021 60 University Introduction for Mentor Graphics tools
3 Art of research and publishing, Dr.Arjun R, VIT 18-June2021 10 Nil Paper writing basics, what to look for while selecting a conference/ journal
4 Scaling effects on Analog and mixed signal circuits: Dr. Purushothaman A, 29-May-2021 53 Nil Basic idea of VLSI domain opportunities for PG aspirants
5 System on Chip Test challenges, Dr. Ramesh 8-May-2021 20 Nil Basics of VLSI domain for PG aspirants
6 Scaling effects on Analog and mixed-signal circuits: Dr. Purushothaman A, Post Doc: MCCI, UCC, Ireland 10-May-2020 215 Nil Basic idea of VLSI domain opportunities for PG aspirants
7 A Workshop on Digital Logic from Scratch using Xilinx FPGA 14-Dec-2019 24 University Digital Design flow
8 Three-Day Faculty Development Programme 13-June-2019 15-June-2019 Amrita Faculty University FDP
Fellowships Received
  • 27thInternational Symposium on VLSI Design and Test (VDAT-2023), BITS Pilani
  • International Test Conference, India 2022, (Received Fellowship & Research Mentorship),
  • International Test Conference, India 2021, (Received Fellowship)
  • International Test Conference, India 2020, (Received Fellowship)
  • International Test Conference, India 2019, (Received Fellowship)
  • International Test Conference, India 2018, (Received Fellowship)
Certifications
  1. Test Synthesis with Genus Stylus Common UI v21.1 Exam from Cadence Design Systems
  2. Genus Low-Power Synthesis Flow with IEEE 1801 v21.1 Exam from Cadence Design Systems
  3. Cadence Genus Synthesis Solution v19.1 (Online) from Cadence Design Systems
  4. Cadence RTL-to-GDSII Flow v3.0 Exam from Cadence Design Systems
  5. TTTC Workshop on VLSI Test and Reliability-Vellore Institute of Technology, Vellore from Siemens Digital Industries Software
Other Recognitions
  • Speaker for IEEE PES Kerala Chapter on the topic: ‘How to execute Successful B. Tech Projects 3.0’, September 20, 2020.
  • Co-presenter for BhAUMika: a device prototype for saving lives during landslides at Sasthrayaan (2018) open house (a Two Day Scientific and Technological Exhibition), Cochin University of Science and Technology organized in collaboration with Rashtriya Uchchatar Shiksha Abhiyan (RUSA), Govt. of India and Govt. of Kerala, conducted on February 27 – 28, 2018.
  • Speaker for KSEBEA on topic ’Use of state machine approach for designs’ connected with Engineers’ Day, September 15, 2017.
Workshops/ Trainings/ Attended
  • Design, Implementation and Verification in VLSI, Sandeepani School of Embedded System Design, Bangalore. April 27, to May 1, 2020.
  • VLSI SATA-2014, Amrita Vishwa Vidyapeetham, Bangalore Campus.
  • Workshop on FPGA based Digital Design organized by Department of Avionics, Indian Institute of Space Science and Technology, Thiruvananthapuram, 2012
  • Faculty Development Program on IC Amplifiers at Amrita Vishwa Vidyapeetham, Amritapuri.
  • Faculty Development Programme on CMOS Design-NIT Calicut. 2012
  • Recent Advances in Computing and Communication Technologies, Govt. Engineering. College Barton Hill, Thiruvananthapuram. 2013
  • Consultation meeting on Energy conservation organized by Kerala State Electricity Board Engineer’s Association.
  • STTP on Design and modeling of advanced analog and digital systems, Govt. Engineering college, Kannur, Kerala. 2013
  • Implementation of Signal Processing Application on FPGA Using Xilinx System Generator at KarunyaUniversity Coimbatore, Tamil Nadu. 2011
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