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Dr. Ganapathi Hegde

Assistant Professor (SG), Department of Electronics and Communication, School of Engineering, Bengaluru

Qualification: M.Tech., Ph.D
ganapathi_hegde@blr.amrita.edu
Research Interest: Computer Algorithms, Very-Large-Scale Integration (VLSI) Systems

Bio Publications Major Research Interests Membership in Professional Bodies Courses Taught Student Guidance
Bio

Dr. Ganapathi Hegde currently serves as Assistant Professor (SG) at the Department of Electronics and Communication, Amrita School of Engineering, Bengaluru.  He received his B.E. degree in Electronics and Communication from the University of Mysore, India, in 1998 and his M.Tech. degree in Digital Electronics from Visweswaya Technological University, Belgaum, India, in 2001. From 2001 to 2005, he worked as a lecturer at the Manipal Institute of Technology, India. Since 2005, he has been working as an Assistant Professor with the Department of Electronics and Communication Engineering, School of Engineering, Amrita Vishwa Vidyapeetham, Bangalore, India. His main research interests are VLSI architectures for video processing, ASIC design, and Low‐Power VLSI design.

  • Ph.D. ( 2018)
    From: Amrita Vishwa Vidyapeetham, INDIA
  • M.Tech. (2001)
    From: V. T.U. Belgaum, INDIA
  • B.E.  (1998)
    From: University of Mysore, INDIA
Publications

Journal Article

Year : 2018

A new approach for 1-D and 2-D DWT architectures using LUT based lifting and flipping cell

Cite this Research Publication : Hegde, G., Reddy, K.S., Shetty Ramesh, T.K., A new approach for 1-D and 2-D DWT architectures using LUT based lifting and flipping cell, AEU-International Journal of Electronics and Communications, 2018, 97, pp. 165–177

Year : 2016

VLSI implementation of the video encoder using an efficient 3-D DCT algorithm

Cite this Research Publication : G. Hegde, Dr. Shikha Tripathi, and Vaya, P. R., “VLSI implementation of the video encoder using an efficient 3-D DCT algorithm”, International Journal of Electronics Letters, vol. 4, pp. 38–49, 2016.

Publisher : International Journal of Electronics Letters, Taylor & Francis.

Year : 2015

Conservative approximation-based full-search block matching algorithm architecture for QCIF digital video employing systolic array architecture

Cite this Research Publication : G. Hegde, Krishna, R. S. Amritha, and Vaya, P., “Conservative approximation-based full-search block matching algorithm architecture for QCIF digital video employing systolic array architecture”, ETRI Journal, vol. 37, pp. 772-779, 2015.

Publisher : ETRI Journal

Year : 2013

A parallel 3-D discrete wavelet transform architecture using pipelined lifting scheme approach for video coding

Cite this Research Publication : G. Hegde and Vaya, P., “A parallel 3-D discrete wavelet transform architecture using pipelined lifting scheme approach for video coding”, International Journal of Electronics, vol. 100, pp. 1429-1440, 2013.

Publisher : International Journal of Electronics

Year : 2012

Systolic array based motion estimation architecture of 3D DWT sub band component for video processing

Cite this Research Publication : G. Hegde and Vaya, P., “Systolic array based motion estimation architecture of 3D DWT sub band component for video processing”, International Journal of Signal and Imaging Systems Engineering, vol. 5, pp. 158-166, 2012.

Publisher : International Journal of Signal and Imaging Systems Engineering

Year : 2012

An efficient 3-dimensional discrete wavelet transform architecture for video processing application

Cite this Research Publication : G. Hegde and Vaya, P., “An efficient 3-dimensional discrete wavelet transform architecture for video processing application”, Journal of Electronics, vol. 29, pp. 534-540, 2012.

Publisher : Journal of Electronics

Conference Paper

Year : 2020

High Throughput Pipelined S-Boxes for Encryption and Watermarking Applications

Cite this Research Publication : S. Jagata, Ganapathi Hegde, and Murty, N. S., “High Throughput Pipelined S-Boxes for Encryption and Watermarking Applications”, in 2020 International Conference on Smart Electronics and Communication (ICOSEC), Trichy, India, 2020.

Publisher : 2020 International Conference on Smart Electronics and Communication (ICOSEC)

Year : 2019

FPGA Implementation of 8-bit SSA Multiplier for designing OFDM Transceiver

Cite this Research Publication : M. Sagar and Ganapathi Hegde, “FPGA Implementation of 8-bit SSA Multiplier for designing OFDM Transceiver”, in 2019 International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, 2019.

Publisher : 2019 International Conference on Communication and Electronics Systems (ICCES)

Year : 2018

Improving the Reliability of Embedded Memories using ECC and Built-In Self-Repair Techniques

Cite this Research Publication : R. Manasa, Ganapathi Hegde, and M. Vinodhini, “Improving the Reliability of Embedded Memories using ECC and Built-In Self-Repair Techniques”, in 2018 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT), Msyuru, India, 2018.

Publisher : 2018 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT)

Year : 2017

An approach for area and power optimization of flipping 3-D discrete wavelet transform architecture

Cite this Research Publication : Ganapathi Hegde, Reddy, K. Srinivasa, and Dr. T. K. Ramesh, “An approach for area and power optimization of flipping 3-D discrete wavelet transform architecture”, in 2017 7th International Symposium on Embedded Computing and System Design (ISED), Durgapur, India, 2017.

Publisher : 2017 7th International Symposium on Embedded Computing and System Design (ISED)

Year : 2015

High performance VLSI architecture for 2-D DWT using lifting scheme

Cite this Research Publication : R. Mithun and Hegde, G., “High performance VLSI architecture for 2-D DWT using lifting scheme”, in 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, 2015.

Publisher : 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015

Year : 2012

An efficient hardware model for RSA encryption system using Vedic mathematics

Cite this Research Publication : R. Bhaskar, Hegde, G., and Vaya, P. R., “An efficient hardware model for RSA encryption system using Vedic mathematics”, in Procedia Engineering, Coimbatore, 2012, vol. 30, pp. 124-128.

Publisher : Procedia Engineering

Year : 2011

An efficient distributive arithmetic based 3-dimensional discrete wavelet transform for video processing

Cite this Research Publication : G. Hegde and Vaya, P., “An efficient distributive arithmetic based 3-dimensional discrete wavelet transform for video processing”, in Proceedings of 2011 International Conference on Process Automation, Control and Computing, PACC 2011, Coimbatore, 2011.

Publisher : Proceedings of 2011 International Conference on Process Automation, Control and Computing, PACC 2011

Major Research Interests
  • VLSI Architectures for Video Processing
  • Computer Architectures
Membership in Professional Bodies
  • IEEE
  • TETE
  • IE
  • ISTE
Courses Taught
  • VLSI Design
  • Pattern Recognition and Algorithms
  • Sensors and Systems
  • Linear Integrated Circuits
  • VLSI Signal Processing
  • Computer System Architectures
  • Digital Signal Processing
Student Guidance

Undergraduate students

Sl. No. Name of the Student(s) Topic Status – Ongoing/Completed Year of Completion
1 K. Teja

B. Vani

Pradeep

 Intelligent safety system for women security using Raspberry Pi Completed 2020
2 Ram Pradeep A

Ranga Sridhar

 Real Time Adaptive Traffic Control System Completed 2020
3 Sampath Kumar

S V Sandeep

S Akhil

 High performance- based face detection system using FPGA Completed 2019
4 Raghava Krishna Manoj Competitive Intelligence Completed 2018
5 M. Tejaswi A Key Account Prioritization Completed 2018
6 N. Chanadana

G. V. Divya Sai

M. V. N. S. Rohita Reshma

 VLSI Implementation of IP Core for 4G long Term Evolution OFDM/FDMA Completed 2018
7 D. Venkateswara Raju

G. Venkata Naga Deepak

K. Jaya Sesha Sai Nikhil

 ANDROID studio applications Completed 2017

Postgraduate Students

Sl. No. Name of the Student(s) Topic Status – Ongoing/Completed Year of Completion
1 Sridevi Jagata High Throughput Pipelined S-Boxes for Encryption and Watermarking Applications Completed 2020
2 Mallapareddi Sagar FPGA Implementation of 8-bit SSA Multiplier for designing OFDM Transceiver Completed 2019
3 Manasa, R Improving the Reliability of Embedded Memories using ECC and Built-In Self-Repair Techniques Completed 2018
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