Year : 2023
Cite this Research Publication :
S Gauri, KN Sreehari, R Bhakthavatchalu, Design and Implementation of a Fully Pipelined and Parameterizable Hardware Accelerator for BLAKE2 Cryptographic Hash Function in FPGA”,2023 3rd Asian Conference on Innovation in Technology (ASIANCON), 1-7
Publisher :
3rd Asian Conference on Innovation in Technology (ASIANCON)
Year : 2023
Cite this Research Publication :
Yadhu Krishnan S, Bhakthavatchalu, Ramesh "Design and Implementation of MIPI I3C master controller SubSystems', 2023 3rd International Conference on Intelligent Technologies, CONIT 2023
Publisher :
Elsevier
Year : 2023
Cite this Research Publication :
Sankar K.S,Geethu R.S,Bhakthavatchalu, Ramesh,"FPGA implementation of Parameterizable Pattern-generator Modules for LBIST applications",2023 4th International Conference for Emerging Technology, INCET 2023
Publisher :
Elsevier
Year : 2023
Cite this Research Publication :
Bhakthavatchal Ramesh, Ajit Anaswar, Geethu R.S," Design and Performance Comparison of X-Masking Models in DFT Applications',https://www.scopus.com/record/display.uri?eid=2-s2.0-85168141371&origin=resultslist&sort=plf-f
Publisher :
Elsevier
Year : 2022
Cite this Research Publication :
Madhulatha Kamma , Jyothika Karasani , Somanathan, Geethu Remadevi , Bhakthavathchalu, Ramesh ,"Reconfigurable Linear Feedback Shift Register",https://www.scopus.com/record/display.uri?eid=2-s2.0-85127327122&origin=resultslist&sort=plf-f
Publisher :
Elsevier
Year : 2022
Cite this Research Publication :
Devika N.K, Bhakthavatchalu, Ramesh, Anantha Krishnan K.A.,"VLSI Implementation of crypto coprocessor using AES and LFSR", https://www.scopus.com/record/display.uri?eid=2-s2.0-85131920256&origin=resultslist&sort=plf-f
Publisher :
Elsevier
Year : 2022
Cite this Research Publication :
Gireesh Akshay, Bhakthavatchalu Ramesh , Devika K.N., "Performance Analysis of Different Types of Delay based PUFs",https://www.scopus.com/record/display.uri?eid=2-s2.0-85131923452&origin=resultslist&sort=plf-f
Publisher :
Elsevier
Year : 2022
Cite this Research Publication :
Anagha B, Kn, Devika, Bhakthavatchalu, Ramesh, "Hardware Security Solutions for Blockchain's Consensus Mechanisms", 2022 6th International Conference on Trends in Electronics and Informatics, ICOEI 2022 - Proceedings
Publisher :
Elsevier
Year : 2022
Cite this Research Publication :
Paulson, Loyied, Bhakthavatchalu, Ramesh, Devika N.K,"Boundary Scan Security Models using Cryptographic Primitives",2022 6th International Conference on Trends in Electronics and Informatics, ICOEI 2022 - Proceedings
Publisher :
Elsevier
Year : 2022
Cite this Research Publication :
Madhulatha, Kamma, Jyothika, Karasani,Harini, Sirikonda Venkata Bala, Somanathan, Geethu Remadevi, Bhakthavathchalu, Ramesh ," Reconfigurable and Parameterizable Pseudorandom Pattern Generators for Built-in Self Test",7th International Conference on Communication and Electronics Systems, ICCES 2022 - Proceedings
Publisher :
Elsevier
Year : 2022
Cite this Research Publication :
Mammenp, Asha, Kn, Sreehari, Bhakthavatchalu, Ramesh, "Implementation of Efficient Hybrid Encryption Technique", 2022 2nd International Conference on Intelligent Technologies, CONIT 2022
Publisher :
Elsevier
Year : 2022
Cite this Research Publication :
Samra S.S, Sreehari K.N, Bhakthavatchalu, Ramesh,"PUF Based Cryptographic Key Generation",2022 2nd Asian Conference on Innovation in Technology, ASIANCON 2022
Publisher :
Elsevier
Year : 2022
Cite this Research Publication :
Bhakthavatchalu Ramesh, Somanathan Geethu Remadevi,"A Proposal for Programmable Pattern Generator and its FPGA implementation", 3rd IEEE International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI SATA 2022
Publisher :
Elsevier
Year : 2022
Cite this Research Publication :
Hudhaifah Ibn Saleem; Geethu R. S. and Ramesh Bhakthavatchalu, "A Programmable and Parameterisable Reseeding Linear Feedback Shift Register," 2022 Second International Conference on Artificial Intelligence and Smart Energy (ICAIS), 2022, pp. 1629-1633, doi: 10.1109/ICAIS53314.2022.9742870.
Publisher :
IEEE
Year : 2022
Cite this Research Publication :
Malini Mukherjee, Geethu R S and Ramesh Bhakthavatchalu, "A Proposal for Design and Implementation of a Low Power Test Pattern Generator for BIST Applications," 2022 Second International Conference on Artificial Intelligence and Smart Energy (ICAIS), 2022, pp. 1520-1524, doi: 10.1109/ICAIS53314.2022.9742920.
Publisher :
IEEE
Year : 2022
Cite this Research Publication :
Ashutosh Agnihotri; Geethu Remadevi Somanathan; Ramesh Bhakthavatchalu, "Design and Implementation of Programmable Multiple Input Signature Register," 2022 Second International Conference on Artificial Intelligence and Smart Energy (ICAIS), 2022, pp. 1536-1540, doi: 10.1109/ICAIS53314.2022.9742968.
Publisher :
IEEE
Year : 2022
Cite this Research Publication :
Doriginti Mohammad, Kanna Rakesh, Geethu Remadevi Somanathan and Ramesh Bhakthavatchalu, "Programmable Variable-Length Pseudo-Random Sequence Generator," 2022 Second International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT), 2022, pp. 1-4, doi: 10.1109/ICAECT54875.2022.9808067.
Year : 2021
Cite this Research Publication :
Vikranth, Chinnapapakkagari Sreenivasa, Mohammad, Doriginti, Somanathan, Geethu Remadevi, Bhakthavatchalu, Ramesh," Analysis of a Novel Reseeding Pattern Generator",Proceedings - 2nd International Conference on Smart Electronics and Communication, ICOSEC 2021
,
Publisher :
Elsevier
Year : 2021
Cite this Research Publication :
Vikranth, Chinnapapakkagari Sreenivasa, Rakesh, Kanna, Jagadeesh, Bodavula, Mohammad, Doriginti, Somanathan, Geethu Remadevi, Bhakthavatchalu, Ramesh, "Design and Analysis of Test Pattern Generator by combining internal and external LFSR", Proceedings of the 5th International Conference on Trends in Electronics and Informatics, ICOEI 2021.
Publisher :
Elsevier
Year : 2021
Cite this Research Publication :
Thomas Annu, Bhakthavatchalu Ramesh, "Implementation of SHA 256 using MATLAB and on FPGA by the Application of Block Chain Concepts",https://www.scopus.com/record/display.uri?eid=2-s2.0-85113297272&origin=resultslist&sort=plf-f
Publisher :
Elsevier
Year : 2021
Cite this Research Publication :
Narasimha, Palla, Krishna, Maddala Vamsi , Somanathan, Geethu Remadevi,Bhakthavatchalu, Ramesh," Design and analysis of gray code generator as test pattern generator", Proceedings of the 6th International Conference on Communication and Electronics Systems, ICCES 2021
Publisher :
Elsevier
Year : 2021
Cite this Research Publication :
Bhakthavatchalu Ramesh ,Sumanth, B. Naga, Naidu P. Shanmukha Naga, Koduri, Pavan Sri Ram, v, Somanathan, Geethu Remadevi,"Logic Obfuscation Technique for Securing Test Pattern Generators",https://www.scopus.com/record/display.uri?eid=2-s2.0-85116708198&origin=resultslist&sort=plf-f
Publisher :
Elsevier
Year : 2021
Cite this Research Publication :
R.S. Geethu, Bhakthavathchalu, R., and Krishnakumar, M., “Balanced Scan Chain Analysis to Improve Fault Coverage in VLSI circuits”, in 2021 6th International Conference on Inventive Computation Technologies (ICICT), Coimbatore, India, 2021.
Publisher :
2021 6th International Conference on Inventive Computation Technologies (ICICT),
Year : 2021
Cite this Research Publication :
S. Naga Naidu P., B., N. Sumanth, Pavan, S. Ram Koduri, M., S. Ram Teja, R.S. Geethu, and Bhakthavatchalu, R., “Secured Test Pattern Generators for BIST”, in 2021 5th International Conference on Computing Methodologies and Communication (ICCMC), Erode, India, 2021.
Publisher :
2021 5th International Conference on Computing Methodologies and Communication (ICCMC)
Year : 2020
Cite this Research Publication :
S. Satya Sri Seeram, Polireddi, S. Naga Naidu, R.S. Geethu, and Bhakthavatchalu, R., “Synthesis of Synchronous Gray Code Counters by Combining Mentor Graphics HDL Designer and Xilinx VIVADO FPGA Flow”, in 2020 International Conference on Communication and Signal Processing (ICCSP), Chennai, India, 2020.
Publisher :
2020 International Conference on Communication and Signal Processing (ICCSP),
Year : 2020
Cite this Research Publication :
R.S. Geethu, Bhakthavathchalu, R., and Krishnakumar, M., “Synthesis of Pseudorandom Number Generator by Combining Mentor Graphics HDL Designer and Xilinx Vivado FPGA Flow”, in Advances in Communication Systems and Networks, Singapore, 2020.
Publisher :
Advances in Communication Systems and Networks,
Year : 2019
Cite this Research Publication :
Narayanan, Aswathy, Murugan, Senthil, Bhakthavatchalu, Ramesh "Low latency max log map based turbo decoder", Proceedings of the 2019 IEEE International Conference on Communication and Signal Processing, ICCSP 2019
Publisher :
Elsevier
Year : 2019
Cite this Research Publication :
Bhakthavatchalu, Ramesh,Devika K.N "Parameterizable FPGA implementation of SHA-256 using blockchain concept", https://www.scopus.com/record/display.uri?eid=2-s2.0-85065558073&origin=resultslist&sort=plf-f
Publisher :
Elsevier
Year : 2019
Cite this Research Publication :
Yadu, Krishnan K, Bhakthavatchalu, Ramesh "Block Level SoC Verification Using Systemverilog",Proceedings of the 3rd International Conference on Electronics and Communication and Aerospace Technology, ICECA 2019
Publisher :
Elsevier
Year : 2019
Cite this Research Publication :
Sasikumar Midhun, Sreehari K.N, Kumar Arjun S, Bhakthavatchalu, Ramesh," Scalable and Rapid Fault Detection of Memories Using MBIST and Signature Analysis", https://www.scopus.com/record/display.uri?eid=2-s2.0-85101402234&origin=resultslist&sort=plf-f
Publisher :
Elsevier
Year : 2019
Cite this Research Publication :
P. Snehal Dilip, R.S. Geethu, and Bhakthavatchalu, R., “Reseeding LFSR for Test Pattern Generation”, in 2019 International Conference on Communication and Signal Processing (ICCSP), Chennai, India, 2019.
Publisher :
2019 International Conference on Communication and Signal Processing (ICCSP),
Year : 2019
Cite this Research Publication :
S. M., K. N. Sreehari, and R., B., “Systolic array implementation of mix column and inverse mix column of AES”, in Proceedings of the 2019 IEEE International Conference on Communication and Signal Processing, ICCSP 2019, 2019, pp. 730-734.
Publisher :
Proceedings of the 2019 IEEE International Conference on Communication and Signal Processing, ICCSP 2019
Year : 2018
Cite this Research Publication :
K. N. Sreehari and Bhakthavatchalu, R., “Implementation of hybrid cryptosystem using DES and MD5”, in 2018 3rd International Conference on Communication and Electronics Systems (ICCES), 2018
Publisher :
2018 3rd International Conference on Communication and Electronics Systems
Year : 2017
Cite this Research Publication :
Devika K.N, Bhakthavatchalu Ramesh, "Design of efficient programmable test-per-scan logic BIST modules", 2017 International Conference on Microelectronic Devices, Circuits and Systems, ICMDCS 2017Volume 2017-January, Pages 1 - 614 December 2017
Publisher :
Elsevier
Year : 2017
Cite this Research Publication :
Muraleedharan Anjana, Bhakthavatchalu Ramesh "Design of interactive paging and locating device for GPS applications " ,Proceedings of the 2017 IEEE International Conference on Communication and Signal Processing, ICCSP 2017
Publisher :
Elsevier
Year : 2017
Cite this Research Publication :
Bhakthavatchalu, Ramesh, Sooraj S " Hamming 3 algorithm for improving the reliability of SRAM based FPGAs", Proceedings of the 2017 IEEE International Conference on Communication and Signal Processing, ICCSP 2017
Publisher :
Elsevier
Year : 2017
Cite this Research Publication :
Devika K.N, Bhakthavatchalu, Ramesh "Design of reconfigurable LFSR for VLSI IC testing in ASIC and FPGA", Proceedings of the 2017 IEEE International Conference on Communication and Signal Processing, ICCSP 2017
Publisher :
Elsevier
Year : 2017
Cite this Research Publication :
Pavithran T.M, Bhakthavatchalu Ramesh "UVM based testbench architecture for logic sub-system verification",Proceedings of 2017 IEEE International Conference on Technological Advancements in Power and Energy: Exploring Energy Solutions for an Intelligent Power Grid, TAP Energy 2017
Publisher :
Elsevier
Year : 2017
Cite this Research Publication :
Sooraj S, Manasy M, Bhakthavatchalu, Ramesh "Fault tolerant FSM on FPGA using SEC-DED code algorithm",Proceedings of 2017 IEEE International Conference on Technological Advancements in Power and Energy: Exploring Energy Solutions for an Intelligent Power Grid, TAP Energy 2017
Publisher :
Elsevier
Year : 2017
Cite this Research Publication :
Bhakthavatchalu Ramesh, Kumar, Mahin Anil, " FPGA based delay PUF implementation for security applications", https://www.scopus.com/record/display.uri?eid=2-s2.0-85050146573&origin=resultslist&sort=plf-f
Publisher :
Elsevier
Year : 2016
Cite this Research Publication :
Murali, Shanmukha, Kumar Juneeth, Kumar Jayanth, Bhakthavatchalu Ramesh, "Design and implementation of izhikevich spiking neuron model on FPGA", 2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings
Publisher :
Elsevier
Year : 2016
Cite this Research Publication :
Kumar, Juneeth, Murali, Shanmukha, Kumar, Jayanth, Bhakthavatchalu, Ramesh " Design and implementation of Hodgkin and Huxley spiking neuron model on FPGA", 2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings
Publisher :
Elsevier
Year : 2016
Cite this Research Publication :
Kiran, N.H.N. Sai, Bhakthavatchalu, Ramesh, "Implementing delay based physically unclonable functions on FPGA", Proceedings of 2016 International Conference on Advanced Communication Control and Computing Technologies, ICACCCT 2016
Publisher :
Elsevier
Year : 2016
Cite this Research Publication :
Devika K.N, Bhakthavatchalu Ramesh, "Programmable MISR modules for logic BIST based VLSI testing", 2016 International Conference on Control Instrumentation Communication and Computational Technologies, ICCICCT 2016
Publisher :
Elsevier
Year : 2016
Cite this Research Publication :
Chandran Pooja, Kumar, P. Pradeep, Bhakthavatchalu Ramesh, " Time of flight measurement system for an ultrasonic anemometer", 2016 International Conference on Control Instrumentation Communication and Computational Technologies, ICCICCT 2016
Publisher :
Elsevier
Year : 2016
Cite this Research Publication :
Chandran, Reshma, Kumar, P. Pradeep, Bhakthavatchalu, Ramesh, "An FPGA based low cost receiver for ultrasonic anemometer " , 2016 International Conference on Control Instrumentation Communication and Computational Technologies, ICCICCT 2016
Publisher :
Elsevier
Year : 2016
Cite this Research Publication :
M. K. Dinesh and Dr. Ramesh Bhakthavatchalu, “Storage memory/NVM based executable memory interface IP for advanced IoT applications”, in 2016 International Conference on Recent Trends in Information Technology, ICRTIT 2016, 2016.
Publisher :
2016 International Conference on Recent Trends in Information Technology, ICRTIT 2016.
Year : 2016
Cite this Research Publication :
J. Kumar, Kumar, J., Murali, S., and Dr. Ramesh Bhakthavatchalu, “Design and implementation of Izhikevich, Hodgkin and Huxley spiking neuron models and their comparison”, in Proceedings of 2016 International Conference on Advanced Communication Control and Computing Technologies, ICACCCT 2016, 2016, pp. 111-116.
Publisher :
Proceedings of 2016 International Conference on Advanced Communication Control and Computing Technologies, ICACCCT 2016, Institute of Electrical and Electronics Engineers Inc.
Year : 2014
Cite this Research Publication :
Dr. Ramesh Bhakthavatchalu, Krishnan, S., Vineeth, V., and Dr. Nirmala Devi M., “Deterministic seed selection and pattern reduction in logic BIST”, in 18th International Symposium on VLSI Design and Test, VDAT 2014, Coimbatore, 2014.
Publisher :
IEEE Computer Society
Year : 2013
Cite this Research Publication :
Bhakthavatchalu Ramesh, Kripalal Ammu, Nair Suchitra, Venugopal Pallavi, Viswanath Meera "Modified FPGA based design and implementation of reconfigurable FFT architecture", Proceedings - 2013 IEEE International Multi Conference on Automation, Computing, Control, Communication and Compressed Sensing, iMac4s 2013
Publisher :
Elsevier
Year : 2013
Cite this Research Publication :
Bhakthavatchalu Ramesh, Karthika V.S, Ramesh Lekshmi, Aamani Budhota "Design of optimized CIC decimator and interpolator in FPGA", Proceedings - 2013 IEEE International Multi Conference on Automation, Computing, Control, Communication and Compressed Sensing, iMac4s 2013
Publisher :
Proceedings - 2013 IEEE International Multi Conference on Automation, Computing, Control, Communication and Compressed Sensing, iMac4s 2013
Year : 2011
Cite this Research Publication :
Dr. Ramesh Bhakthavatchalu, S. Mallia, S., Harikrishnan, R., Krishnan, A., and Sruthi, B., “Low power scheduled alarm system using embedded microcontroller with USB interface”, in 2011 International Conference on Emerging Trends in Electrical and Computer Technology, ICETECT 2011, Chunkankadai, 2011, pp. 610-615.
Publisher :
ICETECT
Year : 2011
Cite this Research Publication :
Dr. Ramesh Bhakthavatchalu and Prem, N., “Low power design techniques applied to pipelined parallel and iterative CORDIC design”, in ICECT 2011 - 2011 3rd International Conference on Electronics Computer Technology, Kanyakumari, 2011, vol. 5, pp. 336-340.
Publisher :
ICECT 2011 - 2011 3rd International Conference on Electronics Computer Technology
Year : 2011
Cite this Research Publication :
Dr. Ramesh Bhakthavatchalu, Deepthy, G. R., Vidhya, S., and Nisha, V., “Design and analysis of low power open core protocol compliant interface using VHDL”, in 2011 International Conference on Emerging Trends in Electrical and Computer Technology, ICETECT 2011, Chunkankadai, 2011, pp. 621-625.
Publisher :
ICETECT
Year : 2011
Cite this Research Publication :
Dr. Ramesh Bhakthavatchalu, N Kareem, A., and Arya, J., “Comparison of reconfigurable FFT processor implementation using CORDIC and multipliers”, in Recent Advances in Intelligent Computational Systems (RAICS), 2011 IEEE, Trivandrum, 2011, pp. 343-347.
Publisher :
IEEE
Year : 2011
Cite this Research Publication :
Dr. Ramesh Bhakthavatchalu, Deepthy, G. R., Vidhya, S., and Nisha, V., “Analysis of low power open core protocol bridge interface using VHDL”, in Recent Advances in Intelligent Computational Systems (RAICS), 2011 IEEE, Trivandrum, 2011, pp. 357-362.
Publisher :
Recent Advances in Intelligent Computational Systems (RAICS), 2011 IEEE
Year : 2011
Cite this Research Publication :
Dr. Ramesh Bhakthavatchalu, Deepthy, G. R., Mallia, S. S., HariKrishnan, R., Krishnan, A., and Sruthi, B., “32-bit reconfigurable logic-BIST design using Verilog for ASIC chips”, in Recent Advances in Intelligent Computational Systems (RAICS), 2011 IEEE, Trivandrum, 2011, pp. 386-390.
Publisher :
Recent Advances in Intelligent Computational Systems (RAICS), 2011 IEEE
Year : 2010
Cite this Research Publication :
Dr. Ramesh Bhakthavatchalu, Deepthy, G. R., and Shanooja, S., “Implementation of re-configurable open core protocol compliant memory system using VHDL”, in 2010 5th International Conference on Industrial and Information Systems, ICIIS 2010, Mangalore, Karnataka, 2010, pp. 213-218.
Publisher :
ICIIS 2010
Year : 2010
Cite this Research Publication :
Dr. Ramesh Bhakthavatchalu, Sinith, M. S., Prem, N., and Jismi, K., “A comparison of pipelined parallel and iterative CORDIC design on FPGA”, in 2010 5th International Conference on Industrial and Information Systems, ICIIS 2010, Mangalore, Karnataka, 2010, pp. 239-243.
Publisher :
2010 5th International Conference on Industrial and Information Systems, ICIIS 2010
