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Dr. Bala Tripura Sundari B.

Associate Professor, Electronics and Communication Engineering, School of Engineering, Coimbatore

Qualification: Ph.D
b_bala@cb.amrita.edu
Google Scholar Profile
Research Interest: Device Modeling & Simulation, Nano Electronics, Very-Large-Scale Integration (VLSI) Design for Reconfigurable Computing, VLSI Signal Processing Architectures and Device Modeling for Nano Electronics.

Bio Publications Education Professional Experience Academic Responsibilities Undergraduate Courses handled Post-Graduate / PhD Courses Handled Participation in Faculty Development / STTP / Workshops /Conferences Organizing Faculty Development / STTP / Workshops /Conferences Academic Research – PhD Guidance Academic Research – PG Projects
Bio

Dr. B. Bala Tripura Sundari joined Amrita in 1998. She obtained her Ph. D. (’13) in the area of VLSI design from Amrita Vishwa Vidyapeetham , M. E.(‘98) degree from PSG College of Technology, Bharathiar Coimbatore,  B. E.(’89) in Electronics and Communication from A. C. C. Technology, Karaikudi, Madurai Kamaraj University.

Her areas of interest include VLSI Design,  VLSI Signal Processing Architectures and Device Modeling for Nano Electronics.

Dr. Bala is an IEEE member and a member of  ISTE, IET. She  has published in peer reviewed journals and   a reviewer of IEEE Nano and electron devices Journal of  electronics  in the areas of VLSI Design and nano electronics.

Publications

Conference Paper

Year : 2017

Modeling Graphene FET Frequency Doubler with Integrated Quantum Capacitance Effects using Guartic Equation Technique

Cite this Research Publication : Dr. Bala Tripura Sundari B. and Hariharan, S., “Modeling Graphene FET Frequency Doubler with Integrated Quantum Capacitance Effects using Guartic Equation Technique”, in IEEE 12th International conference on Nanotechnology Materials and Devices Conference (NMDC), 2017.

Publisher : IEEE 12th International conference on Nanotechnology Materials and Devices Conference

Year : 2017

Modeling 15nm graphene FET with contact resistance effects using channel segmentation technique

Cite this Research Publication : S. Hariharan and Dr. Bala Tripura Sundari B., “Modeling 15nm graphene FET with contact resistance effects using channel segmentation technique”, in Proceedings of IEEE International Conference on Circuit, Power and Computing Technologies, ICCPCT 2017, 2017.

Publisher : Institute of Electrical and Electronics Engineers Inc.

Year : 2017

Design of Tri-Gate Schottky Barrier Graphene Nanoribbon Field Effect Transistor

Cite this Research Publication : K. M. S. Krishna and Dr. Bala Tripura Sundari B., “Design of Tri-Gate Schottky Barrier Graphene Nanoribbon Field Effect Transistor”, in 2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT), 2017.

Publisher : 2017 International Conference on Circuit ,Power and Computing Technologies

Year : 2015

Compact model for switching characteristics of graphene

Cite this Research Publication : Dr. Bala Tripura Sundari B. and R, S., “Compact model for switching characteristics of graphene”, in International Conference on Emerging Trends in Micro & Nanotechnology, 2015.

Publisher : International Conference on Emerging Trends in Micro Nanotechnology

Year : 2014

Towards MuGFETs: A Power Reduction Perspective

Cite this Research Publication : A. Sushmitha, Narthanaa, K., Aravindan, I., Kumar, A. S. Ajay, and Dr. Bala Tripura Sundari B., “Towards MuGFETs: A Power Reduction Perspective”, in Green Computing Communication and Electrical Engineering (ICGCCEE), 2014 International Conference , 2014.

Publisher : ICGCCEE

Year : 2011

Dependence vectors and fast search of systolic mapping for computationally intensive image processing algorithms

Cite this Research Publication : Dr. Bala Tripura Sundari B., “Dependence vectors and fast search of systolic mapping for computationally intensive image processing algorithms”, in IMECS 2011 - International MultiConference of Engineers and Computer Scientists 2011, Hong Kong, 2011, vol. 1, pp. 555-562.

Publisher : IMECS 2011 - International MultiConference of Engineers and Computer Scientists 2011

Journal Article

Year : 2017

DC, Frequency Characterization of Dual Gated Graphene FET (GFET) Compact Model and its Circuit Application – Doubler Circuit

Cite this Research Publication : Dr. Bala Tripura Sundari B. and K Raj, A., “DC, Frequency Characterization of Dual Gated Graphene FET (GFET) Compact Model and its Circuit Application - Doubler Circuit”, IOP Conference Series: Materials Science and Engineering, vol. 225, p. 012016, 2017.

Publisher : IOP Conference Series: Materials Science and Engineering

Year : 2016

Simulation of Carbon Nanotube Field Effect Transistors using NEGF

Cite this Research Publication : S. Aravind, Shravan, S., Shrijan, S., R Sanjeev, V., and Dr. Bala Tripura Sundari B., “Simulation of Carbon Nanotube Field Effect Transistors using NEGF”, IOP Conference Series: Materials Science and Engineering, vol. 149, p. 012183, 2016.

Publisher : IOP Conference Series: Materials Science and Engineering .

Year : 2016

High Level Synthesis for Design Space Exploration

Cite this Research Publication : Dr. Bala Tripura Sundari B. and K, R. Krishnanun, “High Level Synthesis for Design Space Exploration”, ARPN Journal of Engineering and Applied Sciences, vol. 11, pp. 1370-1375, 2016.

Publisher : ARPN Journal of Engineering and Applied Sciences

Year : 2016

Compact graphene field effect transistor modeling with quantum capacitance effects

Cite this Research Publication : Dr. Bala Tripura Sundari B. and K., A. Raj, “Compact graphene field effect transistor modeling with quantum capacitance effects”, ARPN journal of engineering and applied sciences, vol. 11, no. 2, pp. 1347 – 1351, 2016.

Publisher : ARPN journal of engineering and applied sciences

Year : 2015

Modelling and Performance Comparison of Graphene and Carbon Nanotube Based FETs

Cite this Research Publication : Dr. Bala Tripura Sundari B. and Sreenath, R., “Modelling and Performance Comparison of Graphene and Carbon Nanotube Based FETs”, ARPN Journal of Engineering and Applied Sciences(Asian Research Publishing Network (ARPN)), vol. 10, pp. 4147-4154, 2015.

Publisher : ARPN Journal of Engineering and Applied Sciences(Asian Research Publishing Network (ARPN))

Year : 2015

Loop transformation for high level synthesis of iterative algorithms

Cite this Research Publication : Dr. Bala Tripura Sundari B. and Preethi, E. S., “Loop transformation for high level synthesis of iterative algorithms”, International Journal of Applied Engineering Research , vol. 10, pp. 31871-31882, 2015.

Publisher : International Journal of Applied Engineering Research

Year : 2014

Compact Model for Dual Gate Graphene Field-Effect Transistor

Cite this Research Publication : Dr. Bala Tripura Sundari B., Sujoy, S., R, A. Dev S., Vimal, R., and , “Compact Model for Dual Gate Graphene Field-Effect Transistor”, International Journal of Electronics and Communication Engineering (IJECE), vol. 7, pp. 81-88, 2014.

Publisher : International Journal of Electronics and Communication Engineering (IJECE)

Year : 2013

A direct method for optimal VLSI realization of deeply nested n-D loop problems

Cite this Research Publication : Dr. Bala Tripura Sundari B. and T R Padmanabhan, “A direct method for optimal VLSI realization of deeply nested n-D loop problems”, Microprocessors and Microsystems, vol. 37, pp. 610-628, 2013.

Publisher : Microprocessors and Microsystems

Year : 2013

Comparison of Configurations of Data Path Architecture Developed Using Templates

Cite this Research Publication : B. Tripura B Sundari and Krishnan, V., “Comparison of Configurations of Data Path Architecture Developed Using Templates”, Advances in Intelligent Systems and Computing, vol. 174 AISC, pp. 539-548, 2013.

Publisher : Advances in Intelligent Systems and Computing

Year : 2012

Mapping multi-loop nest algorithms on to reconfigurable architecture

Cite this Research Publication : B. Tripura B Sundari, “Mapping multi-loop nest algorithms on to reconfigurable architecture”, Journal of Artificial Intelligence, vol. 5, pp. 142-151, 2012.

Publisher : Journal of Artificial Intelligence

Year : 2012

Design Space Exploration of Deeply Nested Loop 2-D Filtering and 6-level FSBM Algorithms Mapped onto Systolic Array

Cite this Research Publication : Dr. Bala Tripura Sundari B., “Design Space Exploration of Deeply Nested Loop 2-D Filtering and 6-level FSBM Algorithms Mapped onto Systolic Array”, The VLSI Design Journal, vol. 2012, 2012.

Publisher : The VLSI Design Journal

Year : 2012

Design Space Exploration of Deeply Nested Loop 2D Filtering and 6 Level FSBM Algorithm Mapped Onto Systolic Array

Cite this Research Publication : Dr. Bala Tripura Sundari B., “Design Space Exploration of Deeply Nested Loop 2D Filtering and 6 Level FSBM Algorithm Mapped Onto Systolic Array”, VLSI Design , vol. 2012, pp. 15:15–15:15, 2012.

Publisher : Hindawi Publishing Corp

Conference Proceedings

Year : 2016

Compact Model for Switching Characteristics of Graphene Field Effect Transistor

Cite this Research Publication : R. Sreenath and Dr. Bala Tripura Sundari B., “Compact Model for Switching Characteristics of Graphene Field Effect Transistor”, AIP Conference Proceedings, Article number 0200132nd International Conference on Emerging Technologies: Micro to Nano 2015, ETMN 2015., vol. 1724. American Institute of Physics Inc., 2016.

Publisher : Source: AIP Conference Proceedings, Article number 0200132nd International Conference on Emerging Technologies: Micro to Nano 2015, ETMN 2015., American Institute of Physics Inc.

Year : 2015

Power Reduction by Clock Gating Technique

Cite this Research Publication : N. Srinivasan, Prakash, N. S., Shalakha, D., Sivaranjani, D., Dr. Bala Tripura Sundari B., and , “Power Reduction by Clock Gating Technique”, International Conference on SMART GRID Technologies, Procedia Technology 21. Elsevier, pp. 631-635, 2015.

Publisher : Elsevier

Year : 2014

Allocation of Optimal Reconfigurable Array using Graph Merging Technique

Cite this Research Publication : R. Resmi and Dr. Bala Tripura Sundari B., “Allocation of Optimal Reconfigurable Array using Graph Merging Technique”, International Conference on Embedded Systems (ICES), 2014 . Coimbatore; India, pp. 49-54, 2014.

Publisher : International Conference on Embedded Systems (ICES)

Year : 2012

Comparison of configurations of data path architecture developed using template

Cite this Research Publication : Dr. Bala Tripura Sundari B. and Krishnan, V., “Comparison of configurations of data path architecture developed using template”, Advances in Intelligent Systems and Computing, vol. 174 AISC. Springer, Bangalore, Karnataka, India, pp. 539-548, 2012.

Publisher : Springer

Year : 2011

Dataflow Transformation for Optimization of Digital/DSP Circuits

Cite this Research Publication : Ramesh S. R., Dr. Bala Tripura Sundari B., and .N, N., “Dataflow Transformation for Optimization of Digital/DSP Circuits”, Third National Conference on Recent Trends in Communication, Computation & Signal Processing organized by Department of ECE,Amrita School of Engineering, Ettimadai . 2011.

Publisher : Amrita School of Engineering

Year : 2010

Design Space Exploration of Deeply Nested Loop Motion Estimation Algorithm Mapped onto Systolic Array

Cite this Research Publication : B. Tripura Sundari, “Design Space Exploration of Deeply Nested Loop Motion Estimation Algorithm Mapped onto Systolic Array”, International Conference on Communication and Computational Intelligence 2010. pp. 46-52, 2010.

Publisher : International Conference on Communication and Computational Intelligence

Book

Year : 2003

Design Through Verilog HDL

Cite this Research Publication : T. R. Padmanabhan and Dr. Bala Tripura Sundari B., Design Through Verilog HDL. IEEE and John Wiley & Sons, 2003.

Publisher : IEEE and John Wiley & Sons

Education
  • 2013: Ph. D. in VLSI Design
    Amrita Vishwa Vidyapeetham
  • 1998: M. E. in Applied Electronics
    Bharathiar University
  • 1989: B. E. in Electronics and Communication
    Madurai Kamaraj University
Professional Experience
Year Affiliation
July 2013 – Present Associate Professor, Department of Electronics and Communication Engineering, Amrita Vishwa Vidyapeetham
Domain : Teaching, Resaerch
January 2004 – June 2013 Assistant Professor, Amrita Vishwa Vidyapeetham
Domain : Teaching, Research
June 1999 – December 2003 Senior Lecturer, Amrita Inst. of Tec. & Science
Domain : Teaching
June 1998 – May 1999 Lecturer, Amrita Inst. of Tec. & Science
Domain : Teaching
Academic Responsibilities
SNo Position Class / Batch Responsibility
2. Program Coordinator 2014-16, PG VLSI Design VLSI Design co-ordnator-Project co-ordinator, Admissions member
3. Class Adviser 2017 – 21 – B.Tech EIE Class advising, counseling
5. Academic Coordinator 4 plus batch -18-19  4 + year student –academic co-ordination
Undergraduate Courses handled
  1. VLSI System Design
  2. VLSI Design
  3. Digital Circuits and Systems
Post-Graduate / PhD Courses Handled
  1. VLSI Signal Processing (VLSI Design) …
  2. Digital Design (VLSI Design)
  3. Solid State Devices (VLSI Design)
  4. Nanoelectronics
Participation in Faculty Development / STTP / Workshops /Conferences
Title Organization Period Outcome
International Conference in VLSI systems architecture (VLSI SATA 2016) Amrita, Bangalore Dec Project PG and UG in Nanoelectronics
Organizing Faculty Development / STTP / Workshops /Conferences
Title Organization Period Outcome
Research Seminar on Emerging Perspectives in Nanoelectronics R&D on. Department of Electronic and Communication Engineering at Amrita School of Engineering, Coimbatore Amrita Vishwa Vidyapeetham India. September 19 – 20, 2014 Participants attended session by experts in Nano electronics industry and academia.
Academic Research – PhD Guidance
SNo Name of the Scholar Specialization / Title Duration / Registration Status / Year
1. Krishnapriya PN Architectures for Stochastic computing June 2016 Ongoing
2. Anooja B Spectrum sharing Issues in cognitive radio January 2015 Ongoing
Academic Research – PG Projects
SNo Name of the Scholar Programme Specialization Duration Status
1. Sreenivas VLSI Design Nano electronics 2017-18 Ongoing
2. Vineeth B VLSI Design  Functional verification and characterization 2017-18 Completed
3. HafiuddinMd VLSI Design Dual Gate TMDFET model –solid state devices 2017-18 Completed
4. B. SaiSuhas VLSI Design Modeling of carbon nanotube and multi-gate GNR –Solid state devices 2017-18 Completed
5.  S. Hariharan S VLSI Design Effect of Contact Resistance in Graphene FETs –nano- electronics 2016-17 Completed
6 K.MadhuSai VLSI Design Tri gate FET using GrapheneNanoribbon 2016-17 Completed
7. K.L.TejaswiRao VLSI Design  Approximate computing algorithms for multimedia 2016-17 Completed
8. Sanjay S VLSI Design Analog Design in CMOS 2016-17 Completed
9. Arya Raj VLSI Design Graphene FET –Virtual source model 2016-17 Completed
10. RanjaniKrishnanunni K VLSI Design Design Space exploration and trade off study in high level synthesis 2015-16 Completed
11 Sreenath R VLSI Design Advanced nanomaterials based FET modeling for frequency windowing 2014-15 Completed
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