Year : 2023
Design of Voltage Controlled Oscillator Based On Active Inductor For RF Receiver Front End
Cite this Research Publication : Sreelakshmi, V.K. and Chalil, A., 2023, August. Design of Voltage Controlled Oscillator Based On Active Inductor For RF Receiver Front End. In 2023 3rd Asian Conference on Innovation in Technology (ASIANCON) (pp. 1-5). IEEE.
Publisher : IEEE
Year : 2023
FPGA Implementation of Cryptography Using Reversible Logic Gates for Images
Cite this Research Publication : Aparna, V.S. and Chalil, A., 2023, August. FPGA Implementation of Cryptography Using Reversible Logic Gates for Images. In 2023 3rd Asian Conference on Innovation in Technology (ASIANCON) (pp. 1-6). IEEE.
Publisher : IEEE
Year : 2022
An IOT based system for securing ATM machine
Cite this Research Publication : Abhijith, S., Sreehari, K.N. and Chalil, A., 2022, March. An IOT based system for securing ATM machine. In 2022 8th International Conference on Advanced Computing and Communication Systems (ICACCS) (Vol. 1, pp. 1764-1768). IEEE.
Publisher : IEEE
Year : 2022
FPGA Implementation of Area and Speed Efficient CORDIC Algorithm
Cite this Research Publication : Nair, H. and Chalil, A., 2022, March. FPGA Implementation of Area and Speed Efficient CORDIC Algorithm. In 2022 6th International Conference on Computing Methodologies and Communication (ICCMC) (pp. 512-518). IEEE
Publisher : IEEE
Year : 2022
FPGA Implementation of High-Performance Montgomery Modular Multiplication with Adaptive Hold Logic
Cite this Research Publication : Vangapandu, B.N. and Chalil, A., 2022, March. FPGA Implementation of High-Performance Montgomery Modular Multiplication with Adaptive Hold Logic. In 2022 6th International Conference on Computing Methodologies and Communication (ICCMC) (pp. 506-511). IEEE
Publisher : IEEE
Year : 2021
Implementation of Optimized VLSI Architecture for Montgomery Multiplication Algorithm
Cite this Research Publication : Thomas, A., Chalil, A. and Sreehari, K.N., 2021. Implementation of Optimized VLSI Architecture for Montgomery Multiplication Algorithm. In Information and Communication Technology for Competitive Strategies (ICTCS 2020) Intelligent Strategies for ICT (pp. 277-285). Springer Singapore.
Publisher : IEEE
Year : 2021
Modelling of Random Number Generator based on PUFs and LFSR for secret key generation
Cite this Research Publication : Krishnan, R. and Chalil, A., 2021, August. Modelling of Random Number Generator based on PUFs and LFSR for secret key generation. In 2021 Second International Conference on Electronics and Sustainable Communication Systems (ICESC) (pp. 893-897). IEEE.
Publisher : IEEE
Year : 2021
Performance Comparison of Radix-2 FFT Butterfly Unit with Baugh Wooley and Modified Baugh Wooley
Cite this Research Publication : Haridas, K., Sreehari, K.N. and Chalil, A., 2021, August. Performance Comparison of Radix-2 FFT Butterfly Unit with Baugh Wooley and Modified Baugh Wooley. In 2021 Second International Conference on Electronics and Sustainable Communication Systems (ICESC) (pp. 240-245). IEEE.
Publisher : IEEE
Year : 2021
IoT-enabled Geriatric Health Monitoring System
Cite this Research Publication : Akhila, L., Megha, B.S., Santhoshlal, N.M., Sreelakshmi, B., Pradeep, V., Chalil, A. and Sreehari, K.N., 2021, August. IoT-enabled Geriatric Health Monitoring System. In 2021 Second International Conference on Electronics and Sustainable Communication Systems (ICESC) (pp. 803-810). IEEE
Publisher : IEEE
Year : 2021
IoT Based System to Enhance Agricultural Practices
Cite this Research Publication : John, A.P., Anand, S.N., Verma, S., Shukla, S., Chalil, A. and Sreehari, K.N., 2021, August. IoT Based System to Enhance Agricultural Practices. In 2021 Second International Conference on Electronics and Sustainable Communication Systems (ICESC) (pp. 845-850). IEEE
Publisher : IEEE
Year : 2020
VLSI Implementation of Turbo Coder for LTE using Verilog HDL
Cite this Research Publication : V. Akshaya, K. N. Sreehari, and Anu Chalil, “VLSI Implementation of Turbo Coder for LTE using Verilog HDL”, in 2020 Fourth International Conference on Computing Methodologies and Communication (ICCMC), Erode, India, India, 2020
Publisher : 2020 Fourth International Conference on Computing Methodologies and Communication (ICCMC),
Year : 2020
Performance Evaluation of LUTs in FPGA in Different Circuit Topologies
Cite this Research Publication :
Nirmal Vinod, K. V. Abhishek Neelakandan, R. Udith, K. Sayooj Devadas, K. Dinesh, Anu Chalil, and K. N. Sreehari, “Performance Evaluation of LUTs in FPGA in Different Circuit Topologies”, in 2020 International Conference on Communication and Signal Processing (ICCSP), Chennai, India, India, 2020.
Publisher : 2020 International Conference on Communication and Signal Processing (ICCSP)
Year : 2019
Performance Analysis of 6T SRAM Cell on Planar and FinFET Technology
Cite this Research Publication : A. A. Kumar and Anu Chalil, “Performance Analysis of 6T SRAM Cell on Planar and FinFET Technology”, in 2019 International Conference on Communication and Signal Processing (ICCSP), Chennai, India, India, 2019
Publisher : 2019 International Conference on Communication and Signal Processing (ICCSP)
Year : 2018
Publicly Verifiable Digital Watermarking Technique for Copyright Property Protection
Cite this Research Publication :
J. Joseph, Anu Chalil, and Dath, G. G., “Publicly Verifiable Digital Watermarking Technique for Copyright Property Protection”, in 2018 3rd International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, India, 2018.
Publisher : 2018 3rd International Conference on Communication and Electronics Systems
Year : 2018
An Efficient Fault Detection Scheme for Advanced Encryption Standard
Cite this Research Publication : G. G. Dath, Anu Chalil, and Joseph, J., “An Efficient Fault Detection Scheme for Advanced Encryption Standard”, in 2018 3rd International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, India, 2018.
Publisher : 2018 3rd International Conference on Communication and Electronics Systems (ICCES),
Year : 2018
FPGA Implementation of Physical Layer Data Encoding Schemes
Cite this Research Publication :
G. Dath and Anu Chalil, “FPGA Implementation of Physical Layer Data Encoding Schemes”, in 2018 Second International Conference on Inventive Communication and Computational Technologies (ICICCT), 2018
Publisher : 2018 Second International Conference on Inventive Communication and Computational Technologies (ICICCT), 2018
Year : 2017
Performance analysis of montgomery multiplier
Cite this Research Publication : C. Anoop and Anu Chalil, “Performance analysis of montgomery multiplier”, in 2017 2nd International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, 2017
Publisher : 2017 2nd International Conference on Communication and Electronics Systems (ICCES),
Year : 2017
Implementation of power estimation methodology for intellectual property at SoC level
Cite this Research Publication : Anu Chalil, “Implementation of power estimation methodology for intellectual property at SoC level”, in 2017 2nd International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, 2017
Publisher : 2017 2nd International Conference on Communication and Electronics Systems (ICCES)
Year : 2017
FPGA based ToF measurement system for ultrasonic anemometer
Cite this Research Publication : P. Chandran, Anu Chalil, and Pradeepkumar, P., “FPGA based ToF measurement system for ultrasonic anemometer”, in 2017 2nd International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, 2017.
Publisher : 2017 2nd International Conference on Communication and Electronics Systems (ICCES)
Year : 2014
An FPGA Implementation of linear & Circular Convolution
Cite this Research Publication : J. Merin Philip and Anu Chalil, “An FPGA Implementation of linear & Circular Convolution”, in IEEE National Conference on Electrical & Electronics Engineering (NC3E-2014), Banglore, 2014.
Publisher : IEEE National Conference on Electrical & Electronics Engineering
Year : 2014
An FPGA Implementation of linear & Circular Convolution
Cite this Research Publication :
J. Merin Philip and Anu Chalil, “An FPGA Implementation of linear & Circular Convolution”, in IEEE National Conference on Electrical & Electronics Engineering (NC3E-2014), Banglore, 2014.