Anjana J G is currently an Assistant Professor with the Department of Electronics and Communication Engineering at Amrita School of Engineering, Amritapuri. She is doing PhD at NIT Calicut. She has completed an M. Tech. in VLSI Design from Calicut University and B.Tech from University of Kerala. Her area of interest include VLSI, Fabrication, TCAD modeling, Thin Film Transistors and circuit design.
Year : 2022
Cite this Research Publication : Anjana, J.G., Anand, V. and Nair, A.R., 2022. Surface potential based modeling of zinc oxynitride thin film transistors. Flexible and Printed Electronics, 7(3), p.035004
Publisher : Flexible and Printed Electronics
Year : 2022
Cite this Research Publication : Anjana, J.G., Nair, A.R. and Anand, V., 2022, August. A Photo Conductivity simulation of ZnON TFT using ATLAS TCAD. In 2022 Third International Conference on Intelligent Computing Instrumentation and Control Technologies (ICICICT) (pp. 1060-1064). IEEE
Publisher : IEEE
Year : 2022
Cite this Research Publication : Anjana, J.G. and Anand, V., 2022, September. A Study on Deposition Rate and Thickness for ZnON Thin Films. In 2022 4th International Conference on Inventive Research in Computing Applications (ICIRCA) (pp. 207-210). IEEE
Publisher : IEEE
Year : 2020
Cite this Research Publication : Anjana, J.G. and Anand, V., 2020, July. Two dimensional numerical simulation of zinc oxy-nitride thin film transistors. In 2020 International Conference on Electronics and Sustainable Communication Systems (ICESC) (pp. 1052-1055). IEEE.
Publisher : IEEE
Year : 2014
Cite this Research Publication : Anjana, J.G. and Prasanth, M., 2014, May. A three level cache structure. In 2014 IEEE International Conference on Advanced Communications, Control and Computing Technologies (pp. 426-430). IEEE
Publisher : IEEE
