Sonali Agrawal currently serves as Assistant Professor(Sr. Gr.) at Department of Electronics and Communication, Amrita School of Engineering, Banglore campus.
Year : 2016
Cite this Research Publication :
N. Dohare and S. Agrawal, “APB based AHB interconnect testbench architecture using uvm_config_db”, International Journal of Control Theory and Applications, vol. 9, pp. 4377-4392, 2016.
Publisher : International Journal of Control Theory and Applications.
Year : 2021
Cite this Research Publication : P. S. V. N. K. Gupta, Balki, S., Vallabhaneni, M., and Agrawal, S., “Design, Implementation and Performance Comparison of D-Latch Using Different Topologies”, in 6th International Conference on Communication and Electronics Systems (ICCES) 2021, PPG Institute of Technology , Coimbatore , 2021.
Year : 2020
Cite this Research Publication : A. Santhosh and S. Agrawal, “Multipumping-Enabled Multiported SRAM Based Efficient TCAM Design”, in 2020 4th International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech), Kolkata, India, 2020.
Publisher : 2020 4th International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech)
Year : 2020
Cite this Research Publication : U. Meenakshi, Aishwarya, P. M., R. Keerthi, V., and S. Agrawal, “An Efficient Sorting Techniques for Priority Queues in High-Speed Networks”, in 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA), Coimbatore, India, 2019.
Publisher : 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA)
Year : 2020
Cite this Research Publication : M. Lahari and S. Agrawal, “Efficient Floating-Point HUB Adder For FPGA”, in 2020 4th International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech), Kolkata, India, 2020.
Publisher : 2020 4th International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech)
Year : 2020
Cite this Research Publication : B. V. N. Tarun Kumar, Chitiprolu, A., G Reddy, H. Kumar, and S. Agrawal, “Analysis of High Speed Radix-4 Serial Multiplier”, in 2020 Third International Conference on Smart Systems and Inventive Technology (ICSSIT), Tirunelveli, India, 2020.
Publisher : 2020 Third International Conference on Smart Systems and Inventive Technology (ICSSIT)
Year : 2020
Cite this Research Publication : S. Vamsi Ch, Kasyap, S. Aravind, S, S., and Agrawal, S., “Design and Implementation of Power Efficient and fast Full Adders Using Hybrid Logics”, in Sixth International Conference on Emerging Research in Computing, Information, Communication and Applications, ERCICA 2020, Nitte Meenakshi Institute of Technology, Bangalore, 2020.
Publisher : Nitte Meenakshi Institute of Technology, Bangalore
Year : 2019
Cite this Research Publication : M. M. Katti and S. Agrawal, “Design of Power Efficient Fault Tolerant Registers using Modified Hybrid Protection Technique”, in 2019 3rd International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech), Kolkata, India, 2019.
Publisher : 2019 3rd International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech),
Year : 2019
Cite this Research Publication : R. Kumar Arya and S. Agrawal, “Design of Efficient 2–4 Modified Mixed Logic Design Decoder”, in 2019 International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, 2019.
Publisher : 2019 International Conference on Communication and Electronics Systems (ICCES)
Year : 2019
Cite this Research Publication : S. K. Karan, Srikanth, N., and S. Agrawal, “A Robust Code for MBU Correction Till 5-Bit Error”, in 2019 International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, 2019.
Publisher : 2019 International Conference on Communication and Electronics Systems (ICCES)
Year : 2019
Cite this Research Publication : S. Eetha, S. Agrawal, and Neelam, S., “Zynq FPGA based system design for video surveillance with sobel edge detection”, in Proceedings - 2018 IEEE 4th International Symposium on Smart Electronic Systems, iSES 2018, 2019, pp. 76-79
Publisher : Proceedings - 2018 IEEE 4th International Symposium on Smart Electronic Systems, iSES 2018
Year : 2018
Cite this Research Publication : K. R. Varma and S. Agrawal, “High speed, Low power Approximate Multipliers”, in 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI), Bangalore, India, 2018.
Publisher : 2018 International Conference on Advances in Computing, Communications and Informatics
Year : 2018
Cite this Research Publication : P. Avani and S. Agrawal, “Efficient Dynamic Virtual Channel Architecture for NoC Systems”, in 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI), Bangalore, India, 2018.
Publisher : 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI),
Year : 2018
Publisher : Symposium on VLSI Design and Embedded Computing (VDEC’18), co-affiliated with Seventh International Conference on Advances in Computing, Communications and Informatics (ICACCI-2018)
Year : 2018
Publisher : Symposium on VLSI Design and Embedded Computing (VDEC’18), co-affiliated with Seventh International Conference on Advances in Computing, Communications and Informatics (ICACCI-2018)
Year : 2017
Cite this Research Publication : P. Priyadarsi Mahapatra and S. Agrawal, “RSA Cryptosystem with Modified Montgomery Modular Multiplier”, in 2017 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), Coimbatore, India, 2017.
Publisher : 2017 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)
Year : 2017
Cite this Research Publication : N. V. Menon and S. Agrawal, “A Speed Efficient FIR Filter for Reconfigurable Applications”, in 2017 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), Coimbatore, India, 2017.
Publisher : 2017 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)
Year : 2017
Cite this Research Publication :
N. Sowjith, K. Sandeep, S., Sumanth, M., and S. Agrawal, “Low power VLSI architecture for combined FMO/Manchester encoder for reusability and FMO/Manchester codecs”, in 2016 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2016, 2017.
Publisher : 2016 IEEE International Conference on Computational Intelligence and Computing Research,
Year : 2016
Cite this Research Publication :
S. V. Smrithi and S. Agrawal, “A fast architecture for maximum/minimum data finder with address from a set of data”, in 2016 International Conference on Computer Communication and Informatics, ICCCI 2016, 2016.
Publisher : International Conference on Computer Communication and Informatics, ICCCI 2016, Institute of Electrical and Electronics Engineers Inc
Year : 2016
Cite this Research Publication :
N. S., S. Agrawal, and Dr. N.S. Murty, “An architecture for high speed Radix10 division”, in 2016 International Conference on Computer Communication and Informatics (ICCCI), 2016.
Publisher : 2016 International Conference on Computer Communication and Informatics (ICCCI)
Year : 2022
Cite this Research Publication : Chilukuri sai Vamsi, Sanagaram Arvind Kasyap, S saiprateeka, Sonali Agrawal, “Design and Implementation of Power-Efficient and Fast Full Adders Using Hybrid Logics”, Lecture Notes in Electrical Engineering, Volume 790, Pages 119 – 133, 2022.
Year : 2021
Cite this Research Publication : A. Varada and S. Agrawal, "An Efficient SRAM-Based Ternary Content Addressable Memory (TCAM) with Soft Error Correction," 2021 5th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), 2021, pp. 1-6, doi: 10.1109/IEMENTech53263.2021.9614696.
Year : 2021
Cite this Research Publication : Sanjith Reddy P V, P V Sai Sanath Potnuru, T Sai Venkatesh, Sonali Agrawal "Design and Implementation of Efficient Stochastic Number Generator", 2021 Fourth International Conference on Electrical, Computer and Communication Technologies (ICECCT)
| Jan 2004 – Nov 2010 | M.P. Christian College of Engineering and Technology, Bhilai |
| July 2011-Till date | Amrita school of Engineering, Bengaluru |
7 Months internship in Intel, Bengaluru in Layout Design and Verification Team.
Low power/High speed VLSI System Design, Digital Design, Error resilient memory design, Physical design of Integrated Circuits.
| Sl. No. | Name of the Student(s) | Topic | Status – Ongoing/Completed | Year of Completion |
|---|---|---|---|---|
| 1 | Kurla Chandrika, Pooja R. B., Peddinti Twihal | A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic with Complementary n- and p-type Flip-Flops | Ongoing | |
| 2 | Gorrepati Chaithra
Sri, Veera Hanuma S Arpitha Kopparthi, Nuthalapati Harshith |
Low-power High-speed Bidirectional Architecture for Sorting Algorithm | Ongoing | |
| 3 | V. Mani Kantha
P.S.V.N.K. Mani Gupta Sreenidhi Balki |
Bulk driven MCML technique for low power and high-speed applications | Completed | 2021 |
| 4 | Sanjith Reddy P V
Sai Sanath Potnuru Thunguntla Sai Venkatesh |
Efficient Stochastic Number Generators for Stochastic Computing | Completed | 2021 |
| 5 | Saiprateeka Siddabattuni
Sanagaram Aravind Kasyap Sai Vamsi Chilukuri |
Design and implementation of power efficient and fast Hybrid full adders | Completed | 2020 |
| 6 | B.V.N.Tarun Kumar
G.Hemanth Ch.Aravind |
High Speed Radix 4 Serial Multiplier | Completed | 2020 |
| 7 | Vaishnavi | To build an Automation tool to generate register related artifacts | Completed | 2020 |
| 8 | Keerthi Vani
P M Aishwarya U Meenakshi |
A fast, single- instruction-multiple data, scalable priority queue | Completed | 2019 |
| 9 | Karan K
Srikanth N |
4-bit burst error correction codes with quadruple adjacent error correction | Completed | 2019 |
| 10 | K Poorna | Post Silicon characterization and validation of ADuCM4050 | Completed | 2018 |
| 11 | Karthik G Krishnan | Landing of an unmanned Aerial vehicle on a moving target using learning and non-learning approaches | Completed | 2018 |
| 12 | Manoj Kantipudi P Satya Vivek P Sai Raghu Ram Reddy |
Reliable Hamming Matrix Code (RHMC) against multiple cell upsets | Completed | 2017 |
| 13 | Kollipara Sai Sandeep
Mavaluru Sumanth Mavaluru Sumanth |
VLSI Architecture of FM0/Manchester Encoding using SOLs Technique with reusability | Completed | 2016 |
| 14 | R. Sandeep
N. Samyuktha R. Sucharitha |
An Efficient Denoising architecture for Removal of Impulse noise in images | Completed | 2014 |
| Sl. No. | Name of the Student(s) | Topic | Status – Ongoing/ Completed | Year of Completion |
|---|---|---|---|---|
| 1 | Sandeep Kumar Taumar | Design And Implementation Of Efficient Fluctuating Power Logic (FPL) to Mitigate Power Analysis at Cell Level | Ongoing | |
| 2 | V. Anwesh | An Efficient SRAM Based Ternary Content Addressable Memory (TCAM) with Soft Error Correction. | Completed | 2021 |
| 3 | Ashwin Santhosh | Multipumping enabled multiported SRAM based TCAM design on FPGA | Completed | 2020 |
| 4 | M. Lahari | Efficient HUB Floating-pint Adder on FPGA | Completed | 2020 |
| 5 | Meghana M Katti | Design of Power efficient fault tolerant registers using modified Hybrid protection technique | Completed | 2019 |
| 6 | Rohit Kumar Arya | Design of efficient 2-4 modified mixed logic design Decoder | Completed | 2019 |
| 7 | Eetha Sagar | Zynq FPGA based System design for Video surveillance with Sobel Edge Detection | Completed | 2018 |
| 8 | P. Avani | Efficient Dynamic Virtual Channel architecture for NoC | Completed | 2018 |
| 9 | Kamya R Varma | Multi-virtual Sequencer concept for different snapshots in a Testbench | Completed | 2018 |
| 10 | Priyanka P Mahapatra | Design and implementation of RSA Algorithm using Low-Cost High-Performance Carry save Montgomery Modular Multiplier | Completed | 2017 |
| 11 | Sharungbam Shila | Implementation of Discrete wavelet transform using area efficient and low power configurable booth multiplier | Completed | 2017 |
| 12 | Navya V Menon | Low power High speed FIR Filter | Completed | 2017 |
| 13 | Nitiyanka Dohare | APB based AHB Interconnect Testbench Architecture Using uvm_config_db | Completed | 2016 |
| 14 | Neethu S | A Fast architecture for Radix 10 Division | Completed | 2015 |
| 15 | Smrithi S V | A Fast circuit topology for Maximum/Minimum Data finder with address from a set of data | Completed | 2015 |
| 16 | Athira Koranath | Comparison of Different Multiplier Algorithms And 1d-DWT as an Application. | Completed | 2012 |
| 17 | Serene Jose | Single Precision Floating Point Divider Design | Completed | 2012 |
