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Course Detail

Course Name Digital Electronics Laboratory
Course Code 23CSE285
Program B. Tech. in Computer Science and Engineering (CSE)
Semester 3
Credits 1
Campus Amritapuri ,Coimbatore,Bengaluru, Amaravati, Chennai

Syllabus

  1. Logic Gates: Implement logic gates using NAND / NOR.
  2. Boolean functions: using logic gates
  3. Combinational circuits: Mux, De-Mux, Code Converters, Adders & Subtractors
  4. Sequential Circuits: Flip-Flops, Counters, State Machines
Experiments
  1. Verification of Basic Logic Gates.
  2. Realization of Basic Gates using Universal Logic Gates.
  3. Simplification and Realization of a given Boolean Expression i) Using basic gates ii) SOP Using NAND gates only iii) SOP Using NOR gates only iv) POS Using NAND gates only v) POS Using NOR gates only and vi) Compare and analyze the above implementations
  4. Design and verification of Adders and Subtractors.
  5. Design and verification of Parallel Adder / Subtractor.
  6. Design and verification of Binary to Gray code converter and vice versa.
  7. Design and verification of BCD to Excess-3 code converter and vice versa.
  8. Design and verification of 2-bit Magnitude Comparator.
  9. Design and verification of Multiplexers
  10. Implementation and verification of Half adder, full adder, half subtractor and full subtractor using multiplexers.
  11. Design and verification of Flip-flops (D, T and JK flipflop).
  12. Design and verification of shift Registers.
  13. Design and verification of Ring and Johnson Counters.
  14. Design and verification of 4-bit asynchronous Up and Down Counters

Objectives and Outcomes

Course Objectives

  • To provide hands-on experience in realizing simple logic expressions
  • To demonstrate the power of logic function optimization
  • To enable the implementation of combinational and sequential circuits.

Course Outcomes

CO1: Use datasheets & simulation tools effectively

CO2: Realize simple logic circuits

CO3: Design & implement combinational circuits

CO4: Design & implement sequential circuits

CO-PO Mapping

PO/PSO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2
CO
CO1 3 3 2 2 2 2
CO2 3 2 2 2
CO3 3 3 2 2 2 2 2
CO4 3 3 2 2 2 2 2

Evaluation Pattern

  1. Evaluation Pattern: 80:20
    Assessment Internal External
    Mid Sem Examination 20
    *Continuous Assessment Laboratory (CAL) 60
    End Semester 20

    *CAL includes Lab Evaluations, Assignments

Text Books / References

  1. Logic Gates: Implement logic gates using NAND / NOR.
  2. Boolean functions: using logic gates
  3. Combinational circuits: Mux, De-Mux, Code Converters, Adders & Subtractors
  4. Sequential Circuits: Flip-Flops, Counters, State Machines

Experiments

  1. Verification of Basic Logic Gates.
  2. Realization of Basic Gates using Universal Logic Gates.
  3. Simplification and Realization of a given Boolean Expression i) Using basic gates ii) SOP Using NAND gates only iii) SOP Using NOR gates only iv) POS Using NAND gates only v) POS Using NOR gates only and vi) Compare and analyze the above implementations
  4. Design and verification of Adders and Subtractors.
  5. Design and verification of Parallel Adder / Subtractor.
  6. Design and verification of Binary to Gray code converter and vice versa.
  7. Design and verification of BCD to Excess-3 code converter and vice versa.
  8. Design and verification of 2-bit Magnitude Comparator.
  9. Design and verification of Multiplexers
  10. Implementation and verification of Half adder, full adder, half subtractor and full subtractor using multiplexers.
  11. Design and verification of Flip-flops (D, T and JK flipflop).
  12. Design and verification of shift Registers.
  13. Design and verification of Ring and Johnson Counters.
  14. Design and verification of 4-bit asynchronous Up and Down Counters

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