Unit 1
SOP and POS Expressions, Karnaugh Map Simplification – Universal gates, Sequential circuits and combinational circuits, Flip Flops, Registers, Counters, Decoder, Encoder, Multiplexer, De-multiplexer, Arithmetic circuits,
| Course Name | Computer Organization |
| Course Code | 18CSA111 |
| Program | Bachelor of Computer Applications |
| Semester | 2 |
| Year Taught | 2018 |
SOP and POS Expressions, Karnaugh Map Simplification – Universal gates, Sequential circuits and combinational circuits, Flip Flops, Registers, Counters, Decoder, Encoder, Multiplexer, De-multiplexer, Arithmetic circuits,
Computer Organization and Design – Instruction Codes- Computer Registers- Computer Instructions – Instruction Cycle – Memory Reference Instructions – Input Output configuration
Central Processing Unit: Introduction- General Register Organization – Stack Organization – Instruction Formats – Addressing Modes – Data Transfer and Manipulation – Conditional Branch Instructions – Program Interrupts
Pipeline and Vector Processing Parallel Processing – Pipelining – Arithmetic Pipeline – Instruction Pipeline – Vector Processing – Array Processors
Memory Organization Memory Hierarchy – Types of Memory – Main Memory – Auxiliary Memory – Associative Memory – Cache Memory Computer Arithmetic – Introduction – Multiplication Algorithm – Booth’s Algorithm
‘Computer Organization’ is a course offered in the second semester of B. C. A. (Bachelor of Computer Applications) program at School of Engineering, Amrita Vishwa Vidyapeetham, Amritapuri.
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