| Course Name | Computer Organization and Architecture |
| Course Code | 23CSE213 |
| Program | B. Tech. in Computer Science and Engineering (CSE) |
| Semester | 4 |
| Credits | 4 |
| Campus | Amritapuri ,Coimbatore,Bengaluru, Amaravati, Chennai |
Overview and history of computer architecture, combinational vs sequential logic, hardware description languages (VHDL), physical constraints (gate delay, fan-in, fan-out, energy/power). Introduction to Instruction Set Architecture, Processor Architecture with example as ARM & Instruction Set, Single Cycle Datapath Design, Control Hardware, Computer Arithmetic, Floating Point Arithmetic, Design of ALU, Introduction and Performance of Computing system and role of performance.
Introduction to multicycle at a path, Instruction level parallelism, instruction pipelining, Pipelining Technique – Design Issues, Hazards: Structural Hazards, Data Hazards and Control Hazards, Static Branch Prediction, Dynamic Branch Prediction, pipeline hazards and advanced concepts in pipelining.
Storage systems, introduction to memory hierarchy: importance of temporal and spatial locality; main memory organization, cache memory: address mapping, block size, replacement, and store policies; virtual memory system: page table and TLB.
External storage; IO fundamentals: handshaking, buffering, programmed IO, interrupt driven IO; Interrupt handling mechanism, Buses: protocols, arbitration. Introduction to modern processors like GPU and TPU, Parallel Processing.
Course Objectives
Course Outcomes
CO1: Understand the design principles of Instruction Set Architecture (ISA) by taking ARM as reference.
CO2: Understand the design of data and control path in Single Clock Cycle.
CO3: Understand the design of instruction execution using Multiple Clock Cycles and Analyze / Evaluate the performance of processors.
CO4: Understand Pipelined architecture and Design of multi-stage pipeline processor in ARM.
CO5: Apply the working principles of ALU, Memory and I/O in the design of processor.
CO-PO Mapping
| CO | PO1 | PO2 | PO3 | PO4 | PO5 | PO6 | PO7 | PO8 | PO9 | PO10 | PO11 | PO12 | PSO1 | PSO2 | PSO3 |
| 1 | 2 | 3 | 1 | 3 | – | – | – | – | – | – | – | – | 3 | 2 | |
| 2 | 3 | 3 | 3 | 2 | – | – | – | – | – | – | – | – | 3 | 2 | |
| 3 | 2 | 2 | 2 | 3 | – | – | – | – | – | – | – | – | 3 | 2 | |
| 4 | 2 | 2 | 3 | 2 | – | – | – | – | – | – | – | – | 3 | 2 | |
| 4 | 2 | 2 | 2 | 2 | 3 | 2 | 2 | – | – | – | – | – | – | 3 | 2 |
Evaluation Pattern: 50:50
| Assessment | Internal | External |
| Mid-semester | 20 | |
| *Continuous Assessment (CA) | 30 | |
| End Semester | 50 |
*CA includes Quizzes and Tutorials
Textbook(s)
Reference(s)
J.P. Hayes, “Computer Architecture and Organization”, Mc Graw Hill 2017
William Stallings, “Computer Organization and architecture – Designing for performance”, 10th Edition, 2016, Pearson Education.
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