Publication

Abstract : In deep-submicrometer cmos processes, time-domain resolution of a digital signal is becoming higher than voltage resolution of analog signals. This claim is nowadays pushing toward a new circuit design paradigm in which the traditional analog signal processing is expected to be progressively substituted by the processing of times in the digital domain. Within this novel paradigm, digitally controlled delay lines (DCDL) should play the role of digital-to-analog converters in traditional, analog-intensive, circuits. Digital delay locked loops are highly prevalent in integrated systems. The proposed paper addresses the glitches present in delay circuits along with area, power dissipation and signal integrity. The digitally controlled delay lines(DCDL) under study have been designed in a 90 nm CMOS technology 6 layer metal Copper Strained SiGe Low K Dielectric. Simulation and synthesis results show that the novel circuits exhibit no glitches for dual output coarse DCDL with less power dissipation and consumes less area compared to the glitch free NAND based DCDL. The most design intensive component of the DLL is the Digitally Controlled Delay Line (DCDL). A DCDL is a combinational circuit that delays its input by an open loop value that typically has a monotonic relationship with the digital setting input. Such delay value is not precisely defined and is subject to process, voltage, and temperature conditions. The average modern microprocessor contains multiple digital delay locked loops embedded in various subsystems. The vast majority of DCDLs in DLL applications are related to clocking and can also be used in absolute measurement of unknown delays (time to digital conversion).