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Dr. Kamatchi S.

Assistant Professor[Sr Gr], Department of Electronics and Communication, School of Engineering, Bengaluru

Qualification: Ph.D
s_kamatchi@blr.amrita.edu
Google Scholar
Research Interest: ARM Processor ans SOC, VLSI

Bio Publications Professional Appointments Major Research Interests Membership in Professional Bodies Research Awards Invited Talks Courses Taught Research Focus Research Scholar Details Student Guidance
Bio

Dr.Kamatchi S serves as Assistant Professor[Sr Gr] at the Department of Electronics and Communication, Amrita School of Engineering, Bengaluru

Dr.Kamatchi S received her Bachelor’s and Master’s degree in Electronics and Communication Engineering from Anna University, Chennai, and Anna University, Coimbatore, India respectively. She further obtained a Ph.D. degree from Anna University, Chennai.

She has teaching experience of over fourteen years.

She worked at Akshaya College of Engineering for the past 10 years and prior to that she worked at Coimbatore Institute of Engineering and Technology for two and half years. Currently guiding 4 research scholars.

Dr.Kamatchi’s research interests include ARM Processors, Digital design, VLSI Testing, Memory design, Hardware security, and SOC

Education

YEAR DEGREE UNIVERSITY
2018 Ph. D. Anna University, Chennai
2010 M. E. Anna University, Coimbatore
2007 B. Tech. Anna University, Chennai
Publications

Journal Article

Year : 2021

Design of Efficient Low Power Strong PUF for Security Applications

Cite this Research Publication : Akash B Patel, S. Kamatchi, Kaveri Hatti “Design of Efficient Low Power Strong PUF for Security Applications”, ICOSEC 2021 IEEE Conference, which held from 7-9, October 2021 at Kongunadu College of Engineering and Technology, Tamil Nadu, India

Publisher : IEEE

Year : 2021

Design and Development of Extended Hamming code technique for SECDAEC in an audio signal

Cite this Research Publication : Mallidi Sumalatha, M. V. Mahesh Babu, M. L. Sai Teja, and Kamatchi. S “Design and Development of Extended Hamming code technique for SECDAEC in an audio signal”, ICOSEC 2021 IEEE Conference, which held from 7-9, October 2021 at Kongunadu College of Engineering and Technology, Tamil Nadu, India

Publisher : IEEE

Year : 2021

Power Optimization of VLSI Scan Under Test using X-Filling Technique

Cite this Research Publication : A. SwethaPriya and Kamatchi S., “Power Optimization of VLSI Scan Under Test using X-Filling Technique”, IEEE Sponsored International Conference on Emerging Trends in Industry 4.0 (ETI 4.0) held at OP Jindal University, Raigarh, Chhattisgarh, India during 19 - 21, May 2021.

Publisher : IEEE

Year : 2017

Detection and Correction of Multiple Upsets in Memories Using Modified Decimal Matrix Code

Cite this Research Publication : Kamatchi S., C. Vivekanandan, and B. Thilagavathi, “Detection and Correction of Multiple Upsets in Memories Using Modified Decimal Matrix Code”, Journal of Computational and Theoretical Nanoscience, vol. 14, pp. 1543-1547, 2017.

Publisher : Journal of Computational and Theoretical Nanoscience

Year : 2016

An Improved Aging-Aware Reliable Vedic Multiplier with Novel Adaptive Hold Logic Circuits

Cite this Research Publication : Kamatchi S., “An Improved Aging-Aware Reliable Vedic Multiplier with Novel Adaptive Hold Logic Circuits ”, International Journal of Printing, Packaging & Allied Sciences, 2016.

Publisher : International Journal of Printing, Packaging & Allied Sciences

Year : 2016

Design Of Low Power Speculative Han-Carlson Adder

Cite this Research Publication : Kamatchi S., “Design Of Low Power Speculative Han-Carlson Adder”, International Journal For Trends In Engineering And Technology, 2016.

Publisher : International Journal For Trends In Engineering And Technology

Year : 2015

Design of Low Power Asynchronous Parallel Adder

Cite this Research Publication : B. Roseline. R and Kamatchi S., “Design of Low Power Asynchronous Parallel Adder ”, International Journal For Scientific Research and Development, vol. 3, pp. 904-908, 2015.

Publisher : International Journal For Scientific Research and Development

Year : 2015

Efficient Aging-Aware Reliable 8-Bit Booth Multiplier with Novel Adaptive Hold Logic Circuit

Cite this Research Publication : Kamatchi S. and .C.Vivekanandan, D., “Efficient Aging-Aware Reliable 8-Bit Booth Multiplier with Novel Adaptive Hold Logic Circuit”, International Journal of Applied Engineering Research , vol. 10, no. 39, 2015.

Publisher : International Journal of Applied Engineering Research

Conference Paper

Year : 2020

A Secure, Area Efficient Strong Physical Unclonable Function Design using LFSR

Cite this Research Publication : P. Kumar and Kamatchi S., “A Secure, Area Efficient Strong Physical Unclonable Function Design using LFSR”, in 2020 International Conference on Smart Electronics and Communication (ICOSEC), Trichy, India, India, 2020.

Publisher : IEEE

Year : 2019

Comparative Performance Analysis of Karatsuba Vedic Multiplier with Butterfly Unit

Cite this Research Publication : V. Harish and Kamatchi S., “Comparative Performance Analysis of Karatsuba Vedic Multiplier with Butterfly Unit”, in 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA), Coimbatore, India, 2019.

Publisher : 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA)

Year : 2016

Reliable Multiplier Design With Adaptive Filter

Cite this Research Publication : Kamatchi S., “Reliable Multiplier Design With Adaptive Filter ”, in ICETET-2016, 2016.

Publisher : ICETET-2016

Year : 2016

Design And Implementation Of Wireless Communication Based Security System For Railway Purpose Using Fpga

Cite this Research Publication : Kamatchi S., “Design And Implementation Of Wireless Communication Based Security System For Railway Purpose Using Fpga ”, in Icctet-2016 And ICETET-2016, 2016.

Publisher : Icctet-2016 And ICETET-2016

Year : 2016

Design of Vedic Multiplier Using Adaptive Hold Logic by Modifying Razor Flipflop

Cite this Research Publication : Kamatchi S., “Design of Vedic Multiplier Using Adaptive Hold Logic by Modifying Razor Flipflop”, in ICETET-2016, 2016

Publisher : ICETET-2016 (2016)

Year : 2016

An Efficient Design of Low Power Speculatuve Hancarlson Adder Using Concurrent Substraction

Cite this Research Publication : Kamatchi S., “An Efficient Design of Low Power Speculatuve Hancarlson Adder Using Concurrent Substraction ”, in ICETET-2016, 2016.

Publisher : ICETET-2016

Conference Proceedings

Year : 2021

Posit Number Division using Newton Raphson Method

Cite this Research Publication : D. Navaneet Rao, Degala, S. Ram, Charan, G. Sai, and Kamatchi S., “Posit Number Division using Newton Raphson Method”, International Conference on Advances in Electrical, Computing, Communications and Sustainable Technologies (ICAECT 2021). Department of Electrical and Electronics Engineering, Shri Shankaracharya Group of Institutions, SSTC, Bhilai, Chhattisgarh, India, 2021.

Publisher : International Conference on Advances in Electrical, Computing, Communications and Sustainable Technologies (ICAECT 2021).

Book Chapter

Year : 2021

Microgrid Optimization and Integration of Renewable Energy Resources: Innovation, Challenges and Prospects

Cite this Research Publication : Sheeba T. Blesslin,G. Jims John Wessley,V. Kanagaraj,S. Kamatchi,A. Radhika,D.A. Janeera “Microgrid Optimization and Integration of Renewable Energy Resources: Innovation, Challenges and Prospects”, in Integration of Renewable Energy Sources with Smart Grid , Edited by M. Kathiresh A. Mahaboob Subahani and G.R. Kanagachidambaresan, Scrivener Publishing, Wiley(2021)

Publisher : Integration of Renewable Energy Sources with Smart Grid (2021)

Professional Appointments
Year Affiliation
2019 Assistant Professor [Senior Grade]
2010 Assistant Professor
Major Research Interests
  • Hardware and Software security, Digital Design, Design for Testing, Low power VLSI, POSIT number systems, PUF designs and ERC
Membership in Professional Bodies
  • ISTE
Research

Research & Management Experience

  • Teaching Experience-13 years
  • Research Experience-3 years
  • I established innovation lab in association with Testing and Verification solution at Akshaya College of Engineering and Technology
  • I also established research and development lab for VLSI at Akshaya College of Engineering and Technology
Awards

Certificates, Awards & Recognitions

  • Received “Best Teacher Award” in September 5th 2014 through AIMS college, Coimbatore.
  • Received Gold Medal during UG for securing overall first mark in University end semester examinations.
Invited Talks

Keynote Addresses/Invited Talks/Panel Memberships

  • Given a talk about Vedic Mathematics for Engineering students
Courses Taught
  • Electronic Devices and Circuits, Analog Electronic Circuits, Digital Electronics, Signals and Systems, Digital Signal Processing, Microprocessor and Microcontrollers, Data Structures and Algorithm Digital System Design, Design for Test and Testing and BIST
Research Focus
  • Artificial Intelligence applications in hardware security
  • Defect-aware low-power scan-based VLSI testing
  • FPGA based VLSI digital signal processing using Machine Learning Algorithms and Neural Networks
  • Low-powered and high-speed VLSI circuit and System Design using Machine Learning Algorithms and Neural Networks
  • Efficient Error Detection and Correction Techniques using Vedic Mathematics
Research Scholar Details
  1. A.Shruthi(Full time research scholar. Amrita School of Engineering, Bangalore)
  2. Joe Nidhin (Staff Engineer, Western Digital, Bangalore)
  3. A.Swetha Priya(Tech Lead, DFT engineer, LTTS Bangalore)
  4. A.Mohammad Hassan(Assistant Professor, J.D.Engineering College, Nagpur)
Student Guidance

Undergraduate students

Sl. No. Name of the Student(s) Topic Status – Ongoing/ Completed Year of Completion
1 K VENKATA REDDY
M VENKATA KARTHIK SAI
N SAI ROHITH		 DESIGN OF A REVERSE CARRY PROPOGATE FULL ADDER FOR DSP APPLICATIONS Ongoing April-2021
2 M. VENKATA MAHESH BABU
MALLIDI SUMALATHA
MAMIDALA LEELA SAI TEJA		  DESIGN AND DEVELOPMENT OF EXTENDED HAMMING CODE ALGORITHM FOR DECODED  Ongoing  April-2021
 3 Dhage Navaneet Rao

Sai Ram Degala

Ganne Sai Charan

  Design of arithmetic core generator for POSIT number systems  2020
 4 B.Trinadh

G.Yuva Ratnam

G.Prem Sai

 Design of energy quality scalable adder based on Non Zero truncation  Completed  2020
 5 K.K.BHAGAVAN REDDY

K.VAMSI KRISHNA

K.LAKSHMI LIKHITA

 Detection of glucoma using fundus image  Completed  2020
 6 RAKSHITH H

ASHMITA GANGULY

 Air Bag Bench Top Simulator  Completed  2019
 7 Dhawal Mukhul Varma Technology Risk and Cyber Security  Completed  2019
 8 Dhawal Mukhul Varma Technology Risk and Cyber Security  Completed  2019

Postgraduate Students

Sl. No. Name of the Student(s) Topic Status – Ongoing/ Completed Year of Completion
1 Akash M Patel DESIGN OF DELAY BASED FEED FORWARD XOR PUF FOR HARDWARE SECURITY AND TRUST Ongoing June-2021
2 Priyaranjan Kumar A Secure , Area Efficient Strong Physical Unclonable Function Design using LFSR Completed 2020

Research scholars

Sl. No. Name of the Student(s) Topic Status – Ongoing/ Completed Year of Completion
1 A.Swetha Priya DESIGN OF DELAY BASED FEED FORWARD XOR PUF FOR HARDWARE SECURITY AND TRUST Ongoing 2025
2 As. Shruthi Hardware Oriented Security and Trust Ongoing 2024
3 J. Nidhin Jose 3D NAND reliability issues Ongoing 2024
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