Publication

Abstract : Intellectual Property threat is most challenging in the integrated chip manufacturing industry. Outsourcing the chip fabrication to untrusted foundries leads at the risk of intellectual property theft. Logical locking is the most popular countermeasure against the hardware intellectual property threats. In which the design is functionally locked with the added logic gates and thus the logically locked design is accessible only by applying the valid keys. This made the attacker to put all efforts to identify the valid key to unlock the integrated chip through various key-guessing attacks. Hence, an enhanced logical locking with locker-box is proposed to design a secured hardware. This lockerbox is a logical non-linear component, which produces an ambiguous relationship between inputs and outputs. This non-linear mathematical function build a strong hardware against key-guessing attacks. Furthermore, the gates at which the logical locking is implanted plays a vital role as the design overheads like area, power and delay are concerned for any design. In this work, the gates with low observability values are chosen, such that an incorrect key will give an output corruption of 50% as a Hamming distance with minimal design overhead and implementation complexity. The experimental results are validated on ISCAS'85, ISCAS'89 and ITC'99 benchmark circuits. Copyright © 2019 American Scientific Publishers All rights reserved