Publication

Abstract : Traditional verification techniques using Verilog lack flexibility of reusable verification environment and faster time to market. The Universal Verification Methodology (UVM) Class Library provides the building blocks needed to develop reusable verification components and test environments using SystemVerilog. This paper focuses on developing a verification environment using SystemVerilog implementation of UVM for JTAG which will introduce an automated stimulus generating verification environment that checks the debugging functionality of JTAG for any given DUT. UVM based functional verification tries to achieve maximum functional coverage by adding constrained random test cases covering all possible scenarios. whereas, functional coverage model cannot be analyzed in traditional verification environment using Verilog. A functional coverage model is built here to find out whether the verification achieves the expected coverage or not. The coding is done using SystemVerilog and the simulation is done using Questasim.