Publication

Abstract : The future of computing is highly dependent on the reversible logic based logic circuitry because the reversible logic implementation reduces the power dissipated compared to the conventional logic based computing. As the reversible logic is more advantageous in reducing power dissipation, the important and frequently used modules can be designed through this reversible logic. There are special reversible logic gates present which are reversible in nature i.e inputs also can be realized from the outputs and they are selected based on the Quantum cost and Garbage outputs. A Multiply and Accumulate (MAC) unit is one of the most frequently used design in the Digital Signal Processing (DSP) applications and also used in many of the FPGA architectures. Hence reversible implementation of 32 bit MAC unit which is frequently used in digital world is done in this paper. Radix-16 Booth encoded Wallace tree multiplier which gives better results is considered in this MAC unit design. Different types of adders are designed and all combinations are compared. A testable 64-bit reversible PIPO unit is designed which stores the temporary values. The complete design of this MAC unit is done in Verilog HDL and synthesis is done using Cadence RTL Compiler. This design is also implemented on Xilinx Virtex 7 FPGA using Synplify Premier tool.