Publication

Abstract : Network-on-Chip (NoC) has become a cost-effective communication interconnect for Tiled Chip Multicore Processor systems. The communication between cores is done through packet exchange. As the computational intensity of applications increases, the amount of packet exchange between cores will also increase. The improper routing of these packets will result in high congestion thereby degrading the system performance. This marks the need for congestion-aware routing in NoC. In the real world, the applications running in NoC create diverse traffic, which in turn creates challenges in routing. Such challenges have resulted in more researchers relying on machine learning algorithms to tackle them. However, the issues pertaining to storage overhead and packet latency prevail in such methodologies. This paper presents an adaptive routing algorithm DeepNR, which uses a deep reinforcement learning approach. The proposed approach considers network information for state representation, routing directions for actions, and queuing delay for reward function. Experiments carried out on synthetic as well as real-time traffics to demonstrate the effectiveness and efficiency of DeepNR using the Gem5 simulator. The results obtained for DeepNR indicate a reduction of up to 21.25% and 44% in overall packet latency under high traffic conditions on real and synthetic traffic respectively, as compared to the existing approaches. Also, DeepNR achieves a throughput of above 90% in both the traffic scenarios.