Publication Type : Conference Paper
Publisher : 2016 - Biennial International Conference on Power and Energy Systems: Towards Sustainable Energy, PESTSE 2016
Source : 2016 - Biennial International Conference on Power and Energy Systems: Towards Sustainable Energy, PESTSE 2016, Institute of Electrical and Electronics Engineers Inc. (2016)
ISBN : 9781467366595
Keywords : Algorithms, Controllers, Counting circuits, Digital signal processing, Electric drives, Electric inverters, Induction motor drive, Induction motors, Iterative methods, MATLAB, Pulse width modulation, PWM inverter, Renewable energy resources, Sampling rates, Speed control, Structural analysis, SVPWM, Variable frequency drives, Variable speed drives, Voltage control
School : School of Engineering
Department : Electrical and Electronics
Year : 2016
Abstract : Pulse Width Modulated (PWM) inverters are most commonly used for grid interfacing in renewable energy systems and for speed control of induction motors in Variable Frequency Drives (VFD), wherein the control computations are implemented in digital signal controllers (sample-based in nature) and are highly complicated. Sampling interval is a critical parameter in PWM control algorithms, because the controller is required to complete one set of control computations within one sampling interval. This is owing to the fact that PWM control algorithms typically involve several axis transformations during a single sampling interval, and consequently take up thousands of instruction cycles, as the trigonometric transformation equations are implemented in modern processors using iterative procedures. This paper presents the effect of sampling frequency on the performance of a PWM inverter in a VFD for speed control of an induction motor. A step by step procedure for sampling rate selection is also proposed. A simulation study is done using MATLAB/Simulink to analyze the performance of the PWM inverter under variable frequency operation. At a fundamental frequency of 50 Hz, a substantial reduction in the THD, by about 9.12% in the voltage and about 39.01% in the current is observed with the proposed increase in sampling frequency by about ten times. Also, a reduction in the % error in voltage by about 5.3% is observed. © 2016 IEEE.
Cite this Research Publication : K. V. Anusha and Vijayakumari, A., “The effect of sampling rates on the performance of a three phase PWM inverter and choice of appropriate sampling rates”, in 2016 - Biennial International Conference on Power and Energy Systems: Towards Sustainable Energy, PESTSE 2016, 2016.