Course

Unit 1

Introduction to reconfigurable devises – Design flow – Circuit Fabrics – LUTs and IO Blocks -Digital Design for reconfigurable hardware – High Level System Architecture and Specification:

Unit 2

Hardware description languages – Hierarchical Modeling Concepts – Behavioural modelling and simulation – HDL Coding Style- Lexical Conventions- Ports and Modules– Operators-Gate Level Modeling – Compiler Directives-Test Bench- Tasks & Functions – Procedural continuous assignments- Synthesis of Combinational Circuits: Behavioral, Data Flow and Structural Realization– Design of combinational and sequential subsystems

Unit 3

Case Study of RTL Design for reconfigurable hardware – Interpreting Synthesis and Implementation reports Design of data path and controller subsystems – FIFOs – Memory controllers – DSP blocks –Block RAMs – Synthesis issues – System Level synthesis from high level languages Block-based design flow – Case study of block-based design of a digital system – Reconfigurable fabrics and bus interfaces.

Prerequisites: Digital Systems

Course Objectives

• To model the digital systems using concurrent languages to suit reconfigurable system
• To gain fundamental knowledge and understanding of the principles and practice in reconfigurable architecture and computing

Course Outcomes

• CO1: Understand synthesizable modelling of digital subsystems.
• CO2: Formulate architecture of systems at the RTL abstraction.
• CO3: Implement digital systems in reconfigurable platforms and evaluate them based on tool reports
• CO4: Employ custom and block design to realize embedded systems. 

CO-PO Mapping

Text Book(s)

1. Kaihui Tu , Xifan Tang , Cunxi Yu , Lana Josipovi? , Zhufei Chu , “FPGA EDA – Design Principles and Implementation”, Springer, 1st edition, 2024. 
2. Marcin Kubica , Adam Opara , Dariusz Kania, “Technology Mapping for LUT-Based FPGA”,Springer, 1^st edition, 2022. 
3. Hideharu Amano, “Principles and Structures of FPGAs”, Springer, 1^st edition, 2018. 

Reference(s)

1. Michael D Ciletti, “Advanced Digital Design with the Verilog HDL”, Second Edition, Pearson, 2017.
2. Samir Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis”, Second Edition, Pearson, 2003.
3. Scott Hauck?and? Andre DeHon ,”Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation” , Morgan Kaufmann Publishers In; 1st edition, 2007.