Publication Type : Journal Article
Publisher : ACM Trans. Reconfigurable Technol. Syst.
Source : ACM Trans. Reconfigurable Technol. Syst., ACM, Volume 6, Number 4, New York, NY, USA, p.14-21 (2013)
Url : http://doi.acm.org/10.1145/2535934(link is external)
Keywords : adaptive control, ASIC, FPGA, parallel hardware, reconfigurable computer, self-tuning regulator
Campus : Coimbatore
School : School of Engineering
Department : Electrical and Electronics
Verified : Yes
Year : 2013
Abstract : The self-tuning regulator (STR) is a popular adaptive control algorithm. A high-performance computer is required for its implementation due to the heavy online computational burden. To extend STR for more real-time applications, a parallel hardware implementation on a low-cost reconfigurable computer is presented. The hardware was incorporated with multistage matrix multiplication (MMM) and trace technique to enhance the processing speed. This design was deeply pipelined to achieve high throughput. The algorithm was prototyped on a Xilinx field-programmable gate array (FPGA) device with a maximum operating frequency of 210.436 MHz. Application-specific integrated circuit (ASIC) implementation of STR was reported.
Cite this Research Publication : T. Ananthan and Vaidyan, M. V., “A Reconfigurable Parallel Hardware Implementation of the Self-Tuning Regulator”, ACM Trans. Reconfigurable Technol. Syst., vol. 6, pp. 14-21, 2013.