Publication

Abstract : In practical applications, where chip area and power consumption are the prime concerns, the hardware implementation with the lower computational complexity of a structure is one of the major issues. Time multiplexing and bit serial processing are useful methods to reduce the hardware requirement. However, the delay elements cannot be reduced by using this method so that significant chip area is occupied. Therefore, in this paper, we developed a delay efficient extended version of the generalized rational sampling rate conversion polyphase FIR filter without any adverse effect on Multiplier/Adder complexity. We also calculated the required number of delay elements ( ) which are involved in the presented structure. We foundDa significant reduction in delay elements in comparison to the generalized rational sampling rate conversion polyphase FIR filter. In addition, we show that, if β > (M - 1)(L- 2) , our presented approach always used lesser delay elements compared with an existing similar approach.