Publication

Abstract : Low Noise Block-down Converter is a crucial and an essential element in Radio Frequency receiver design. It magnifies the received weak Radio Frequency signal with minimum noise level. Designing Low Noise Block-down Converter with CMOS technology provides many advantages such as low power requirement, low cost and higher integration. This paper proposes the design of Low Noise Block-down Converter using 0.13µm CMOS technology. The proposed Low Noise Block-down Converter has two cascaded Common-Source (CS) stages. The cascaded stages provide high gain with less noise figure. A matching component called inter-stage inductor which is placed between the two stages of Block-down Converter. An inter-stage inductor can provide improved input return loss and gain due to careful optimization. By using the proposed topology Block-down Converter achieves maximum gain of 35.603 dB, input return loss of-27.690 dB, output return loss of-28.143 dB, reverse isolation of-41.211 dB, noise figure of 1.712 dB and stability factor of 1.216 is achieved at 1 GHz. The designed Low Noise Block-down Converter is simulated in ADS tool.