Publication Type : Conference Paper
Publisher : IEEE
Source : In 2017 International Conference on Networks & Advances in Computational Technologies (NetACT) 2017 Jul 20 (pp. 86-89). IEEE
Url : https://ieeexplore.ieee.org/document/8076746
Campus : Chennai
School : School of Engineering
Department : Electronics and Communication
Year : 2017
Abstract : This paper, proposed a hybrid full adder with low power and less area using 8 transistors. Majority not gate and GDI techniques are collectively used for design this hybrid full adder. Some beforehand composed cells endure from non-full swing output, low speed, and high power utilization issues. While the new full adder has insignificant range overhead, it has enhanced the power Utilization of the circuit when contrasted with other full adder circuit. We have verified this full adder by utilizing cadence virtuoso gpdk 180nm technology at 1.2V supply voltage.
Cite this Research Publication : Thenmozhi V, Muthaiah R. “Optimized low power full adder design”, In 2017 International Conference on Networks & Advances in Computational Technologies (NetACT) 2017 Jul 20 (pp. 86-89). IEEE.