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High-Speed Power Allocation in NOMA System using FPGA based DNN

Publication Type : Journal Article

Publisher : Journal of Circuits, Systems and Computers

Source : Journal of Circuits, Systems and Computers, Vol. 33, No. 14, 2420004 (2024)

Url : https://www.worldscientific.com/doi/10.1142/S0218126624200044?srsltid=AfmBOorDGtDZBrj7bCqicUfTvm30kMKBwcQufQmRZ040_E9VFM8d1CoG

Campus : Coimbatore

School : School of Artificial Intelligence

Year : 2024

Abstract : Artificial Intelligence (AI) is rapidly transforming the healthcare, finance and transportation industries. This paper presents a field-programmable gate array (FPGA)-based neural network accelerator (NNA) design for power allocation in downlink nonorthogonal multiple access (NOMA) networks. The proposed hardware accelerator effectively cuts computational costs while delivering performance on par with the highest sum capacity. Numerical results show that this NNA offers a remarkable computational speed increase of up to 99% compared to the conventional exhaustive search method. Furthermore, the deep learning (DL) model achieved high accuracy (0.92 training, 0.93 testing), and the hardware accelerator design for this DL inference model was implemented on the PYNQ-Z2 board-constrained edge device to predict power allocation coefficients in NOMA systems.

Cite this Research Publication : Yanamala, Rama Muni Reddy, and Muralidhar Pullakandam. "High-Speed Power Allocation in NOMA System using FPGA based DNN." Journal of Circuits, Systems and Computers, Vol. 33, No. 14, 2420004 (2024)

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