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An Area-Efficient VLSI Architecture with Ladner-Fischer PPA for High-Speed Pseudo-Random Bit Generation

Publication Type : Conference Paper

Publisher : IEEE

Source : 15th ICCCNT 2024: 15th International IEEE Conference on Computing Communication and Networking Technologies.(paper yet to be published).

Campus : Chennai

School : School of Engineering

Department : Electronics and Communication

Year : 2024

Abstract :

Cite this Research Publication : A.C. SakkthiSaranya, P. Maran and Sita Devi Bharatula, B. Naresh Kumar Reddy, “An Area-Efficient VLSI Architecture with Ladner-Fischer PPA for High-Speed Pseudo-Random Bit Generation” in 15th ICCCNT 2024: 15th International IEEE Conference on Computing Communication and Networking Technologies.(paper yet to be published).

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