Publication Type : Patents
Source : Volume US6933219 B1, Number US 10/716,209 (2005)
Url : http://www.google.com/patents/US6933219
Campus : Amritapuri
School : Centre for Cybersecurity Systems and Networks, School of Engineering
Center : Cyber Security, TBI
Department : cyber Security
Year : 2005
Abstract : pThe invention includes an apparatus and a method of manufacturing such apparatus using a damascene process. The method includes the step of patterning a layer disposed over a substrate to include a line and space pattern. The line and space pattern in the layer includes at least one space comprising a width dimension of a feature to be formed. The feature may be, e.g., a wordline(s)/gate electrode(s). Additionally, the sidewalls of the feature, e.g., the wordline(s)/gate electrode(s) include relatively smooth surfaces./p
Cite this Research Publication : Dr. Krishnashree Achuthan, Lingunis, E. H., Van Ngo, M., Tabery, C., and Yang, J. Y., “Tightly spaced gate formation through damascene process”, U.S. Patent US 10/716,2092005
