Publication Type : Patents
Source : (2006)
Url : http://www.google.com/patents/US7125776
Campus : Amritapuri
School : Centre for Cybersecurity Systems and Networks, School of Engineering
Center : Cyber Security, TBI
Department : cyber Security
Year : 2006
Abstract : A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial “rough” planarization and then a “fine” planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.
Cite this Research Publication :
Dr. Krishnashree Achuthan, Ahmed, S. S., Wang, H. H., and Yu, B., “Multi-step chemical mechanical polishing of a gate area in a FinFET”, 2006
