Publication Type : Conference Paper
Publisher : Recent Advances in Intelligent Computational Systems (RAICS), 2011 IEEE
Source : Recent Advances in Intelligent Computational Systems (RAICS), 2011 IEEE, IEEE, Trivandrum, p.386-390 (2011)
Url : https://ieeexplore.ieee.org/abstract/document/6069340
Campus : Amritapuri
School : School of Engineering
Department : Electronics and Communication
Year : 2011
Abstract : The BIST technique for logic circuits improves access to internal signals from primary input/outputs. This paper presents programmable logic BIST architecture for testing ASIC chips. The scheme is based on STUMPS [6] (Self Test Using MISR [4, 6] and Parallel Shift register) architecture which uses an on-chip circuitry to generate the test patterns and analyze the responses with no or little help from an ATE. External operations are required only to initialize the Built-in tests and to check the test results. The system is synthesized in Xilinx ISE 10.1 to get the frequency of operation and in Design Compiler for timing Analysis. Multi Voltage design for power reduction is successfully implemented.
Cite this Research Publication : Dr. Ramesh Bhakthavatchalu, Deepthy, G. R., Mallia, S. S., HariKrishnan, R., Krishnan, A., and Sruthi, B., “32-bit reconfigurable logic-BIST design using Verilog for ASIC chips”, in Recent Advances in Intelligent Computational Systems (RAICS), 2011 IEEE, Trivandrum, 2011, pp. 386-390.