Programs
- M. Tech. in Automotive Engineering -
- B. Sc. Clinical Nutrition, Dietetics, and Food Science - Undergraduate
Publication Type : Conference Paper
Publisher : IEEE
Source : Recent Advances in Intelligent Computational Systems (RAICS), 2011 IEEE, IEEE, Trivandrum, p.343-347 (2011)
Url : https://ieeexplore.ieee.org/document/6069331/authors#authors
Campus : Amritapuri
School : School of Engineering
Department : Electronics and Communication
Year : 2011
Abstract : In this work, two different methodologies for the implementation of a Fast Fourier transform processor: FFT using CORDIC and FFT using Multiplier are investigated. Reconfigurable FFT using radix-2 Decimation in frequency technique is chosen for the comparison. In terms of area and power, both the implementations were analyzed. Coordinate Rotation Digital Computer (CORDIC) is widely used in DSP applications. It utilizes only add and shift operations instead of multipliers. Both CORDIC and multiplier are employed here for twiddle factor multiplication. The experimental result shows that the multiplier based FFT implementation has lower area and power consumption, as compared to CORDIC based implementation.
Cite this Research Publication : Dr. Ramesh Bhakthavatchalu, N Kareem, A., and Arya, J., “Comparison of reconfigurable FFT processor implementation using CORDIC and multipliers”, in Recent Advances in Intelligent Computational Systems (RAICS), 2011 IEEE, Trivandrum, 2011, pp. 343-347.