Publication

Abstract : Data path circuits play a vital role in today's processors. Data path, which defines the structural model for interconnection of resources, needs to be flexible. It consists of a computing architecture modeled by a set of virtual templates. The focus of this work is to obtain the efficient configuration of the templates in order to map data intensive applications. The resource constrained scheduling process is employed to schedule the operations pertaining to different configurations. To achieve this scheduling, the data flow graph is modeled by grouping the resources for different configurations as a vertex cover model. Data intensive applications involve large amounts of data reuse and the number of registers and ports required is determined for each configuration. The number of registers, ports and latency are measures of efficiency of the configuration and using these measures the most efficient configuration of the templates to map an application is determined. © 2013 Springer.