Publication Type : Journal Article
Source : International Journal of Mathematical Modelling and Numerical Optimization, Vol. 7, No.1, pp 83-96, 2016
Url : https://www.inderscienceonline.com/doi/abs/10.1504/IJMMNO.2016.074374
Campus : Coimbatore
School : School of Engineering
Department : Electronics and Communication
Year : 2016
Abstract : This paper presents a new zero suppressed binary decision diagram (ZBDD)-based approach for obtaining larger number of relaxed bits. These test sets find major application in reducing the power consumed during testing. Experiments performed on single and multiple stuck-at faults using ZBDDs show better results in terms of percentage of relaxation over the existing comparable BDD-based approaches. Moreover using these relaxed test vectors and by suitable X-filling methods average switching activity (ASA) of the circuit can be reduced, which will reduce the power dissipation during testing.
Cite this Research Publication : Navya Mohan, J.P. Anita, “A Zero Suppressed Binary Decision Diagram based test set relaxation for single and multiple stuck-at faults” in the International Journal of Mathematical Modelling and Numerical Optimization, Vol. 7, No.1, pp 83-96, 2016