Publication

Abstract : Automatic Test Pattern Generation (ATPG) is the most useful technique for the testing of VLSI designs. In recent times with the increase in the size and complexity of designs, the probability of the occurrence of defects also increases. There-fore testing has become very difficult for complex circuits or designs such as System On Chips (SOC). The solution to this problem is the Embedded Deterministic Test (EDT) which involves in addition of some logic structures to the complex designs to minimize the total cost of the test, the volume of the test and memory usage of ATE (Automatic Test Equipment). In this paper, the analysis of ISCAS’89 benchmark circuits are done by using Embedded Deterministic Test (EDT) to improve the test coverage. Retargeting stage is proposed in-order to compact the test sets produced during ATPG.