Publication

Abstract : In the current multi-core processors, also called System on Chip (SoC), the number of components used in it is increasing in recent days. This indicates a situation that the use of buses is no longer efficient. Now comes the Network on Chip (NoC) with a way to solve this problem. Owing to various noise interference, NoC encounters a huge amount of reliability issues. In nanoscale technology, this issue leads to higher delay and power consumption. To reduce the impact of reliability issues, an error correction coding technique is presented in this paper. Joint Crosstalk Avoidance with Eight Bit Burst Error Correction (JCAEBBEC) is a burst error correction technique followed by duplication in order to avoid crosstalk along with decoding logic that detects and corrects errors. Further, this technique corrects random errors up to 7 bits with approximately 91 % correction capability. Technique corrects burst errors up to 16 bits with 100% correction capability alongside providing crosstalk avoidance. Furthermore, the implementation results show that the JCAEBBEC technique attains lesser area, power and delay compared with the existing techniques.