Publication

Abstract : This manuscript describes the design of a wideband Cascode Low Noise Amplifier (LNA) using Verilog-A models and several passive components. In this paper, look up table (LUT) based Verilog-A models for GAA-JLFET (Gate All Around Junctionless FET) and GAA-NC-JLFET (Gate All Around Negative capacitance Junctionless FET) are developed with reference to their TCAD device simulation results. The models are then integrated into the Cadence EDA tool so that the proposed devices may be utilized in circuit simulation. The noise performances of the GAA-NC-JLFET based LNA have been investigated and compared with GAA-JLFET based LNA.