Publication

Abstract : The field of VLSI design faces the challenge of identifying the possible designs that simultaneously optimize the multiple conflicting objectives such as area, latency, and power. The applications involving high-level synthesis (HLS) tend to engender huge design space due to the pragmas applied in the behavioral description. Therefore, the exhaustive search of Pareto-optimal designs in such HLS applications becomes infeasible due to the computing cost involved. To address this challenge, we propose N-PIR, a Neighborhood-based Pareto iterative refinement approach for design space exploration (DSE) that forms the neighborhoods within the underlying design space by applying an active learning technique and assigns them the ranks. The neighborhoods are explored in the order of their rank for predicting Pareto optimal solutions. The key features of N-PIR include (1) neighborhood creation within the design space through an active learning strategy guided by an uncertainty threshold parameter u; (2) rank assignment to the neighborhoods based on a ranking score; and (3) exploration of neighborhoods in prioritized order (highest-ranked first) for the identification of Pareto optimal designs. N-PIR can produce a better level of accuracy than IRF-TED and IRF-rand by spending the same amount of evaluations. Also, to reach the same level of accuracy, there is a significant amount of savings (range of 7.84% to 46.25%) in the number of evaluations. Furthermore, our experiments show that N-PIR is at par with lattice-traversing and can outperform the cluster-based heuristic and Q-PIR within 10% and 25% of the synthesis budget, respectively.