Publication

Abstract : Memory is a component, playing a significant role in electronic systems. The use of static random access memories (SRAMs) is increasing in multimedia and system on chip applications. The key challenge faced by SRAMs is soft errors induced by the radiation that cause the change of values in memory cells. Error correction codes (ECCs) are used to face this challenge. As the technology is scaling down the chances of multiple bit upsets(MBUs) is increasing. So ECCs with higher correction ability are needed. Many ECCs have been proposed to face the challenge of MBUs. Some of them are SEC-DED codes, QAEC codes, FUEC-QUAEC codes. In this paper, we are presenting ECCs that has same redundancy as recently proposed FUEC-QUAEC codes [1] and can correct all the errors till 5-bit adjacent error. The procedure for encoding and decoding of proposed codes is presented. The encoder and decoder have been implemented using 45nm library and compared with QAEC codes, showing that proposed codes have better error correction capability with moderate delay over head and low power consumption than OAEC codes.