Publication

Abstract : Error correcting codes are widely used to protect memories from radiation induced soft errors. With the advancement of the technology node, soft errors affect more than one bit in memory, as the circuitry is closely packed on a smaller area. Single Error Correction and Double Error Detection (SEC-DED) codes ensures that the contents of the memory gets rectified if corrupted. The Reduced Parity SEC-DED (RP SEC-DED) architecture that uses three blocks of SEC-DED is proposed here that detects six error bits and correct double bit error in first and second block and single bit error in the third SEC-DED block using 15-bits of parity. The input data word is assumed to be of 32-bits. The architecture is implemented using Verilog Hardware Description Language (HDL) in Xilinx Vivado® Design Suite V14.7. The comparative analysis is carried out to determine the number of parity bits used, area, power consumption, delay and the total number of logic gates used with the help of Cadence® Genus™ Synthesis Solution Version 17.2 tool at 45 nm technology with supply voltage of 1 V. The comparative analysis shows that there is a decrease in the number of parity bits used by 4 bits, 14.99% of decrease in area, 3.20% drop in power consumption, 18.48% reduction in delay and reduction of 39 logic gates used in the proposed RP SEC-DED architecture over the existing SEC-DED with DS based Architecture.