Publication Type : Conference Paper
Publisher : 2018 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques
Source : 2018 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT), IEEE, Msyuru, India (2018)
Url : https://ieeexplore.ieee.org/abstract/document/9001509
Campus : Bengaluru
School : School of Engineering
Department : Electronics and Communication
Year : 2018
Abstract : System on Chip (SoC) process technology is shrinking day by day resulting in increased complexity. In the presence of faults, the reliability of embedded memories in deep submicron technology is becoming a significant challenge. Embedded Memories are highly prone to soft errors and hard faults. Hence, hard repair techniques combined with Error Correction Codes (ECCs) can improve the reliability of embedded memories. An integrated ECC and Built-In Self-Repair (BISR) technique is proposed in this paper can correct 8 faulty bits for a 16-bit input. Higher error correction and repair capability gives the higher reliability. The proposed integrated ECC and BISR has less area and more faulty bit correction capability compared to Enhanced Built -In Self-Repair (EBISR) technique.
Cite this Research Publication : R. Manasa, Ganapathi Hegde, and M. Vinodhini, “Improving the Reliability of Embedded Memories using ECC and Built-In Self-Repair Techniques”, in 2018 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT), Msyuru, India, 2018.