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Architecture of Parallel CRC Encoder Using State Space Transformations

Publication Type : Conference Paper

Publisher : 2018 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT),

Source : 2018 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT), IEEE, Bengaluru, India (2018)

Url : https://ieeexplore.ieee.org/abstract/document/8493862

Campus : Amritapuri

School : School of Engineering

Department : Electronics and Communication

Year : 2018

Abstract : Linear Feedback shift Registers (LFSRs) are widely used in encoders like Cyclic Redundancy Check (CRC) for generating error detecting codes. In order to achieve high speed communication, parallel processing is performed in the serial CRC. Since this method increases the circuit complexity, the speed gets limited. State space transformation is a method that can be used to reduce the circuit complexity. Therefore, an efficient transformation matrix is needed in this method. In this paper, a method to construct a transformation matrix and an approximate searching algorithm to generate certain vectors, which are used in transformation matrix are implemented.

Cite this Research Publication : L. S. Prabha and R.S. Geethu, “Architecture of Parallel CRC Encoder Using State Space Transformations”, in 2018 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT), Bengaluru, India, 2018.

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