Publication

Abstract : Blind source separation is a method to separate source signals from mixed signals without any data loss”. This technique has recently drawn a lot of attention in the field of Space research. This paper presents an efficient implementation of the Blind source separation algorithm [FASTica] using FPGA and its optimization. In general independent component analysis[ICA] algorithm separates the source signal from mixed-signal by finding a linear transformation that can maximize the mutual independence of the mixture. FASTica algorithm is the advanced version of the ICA algorithm.FASTica algorithm measures the non-gaussianity using the kurtosis algorithm to find the independent source of their mixture. Blind source separation algorithms are highly computational complex in nature[Vector multiplication, matrix multiplication, Matrix inverse, etc.], To provide high computing power for the algorithm while implementing we are using hardware called FPGA, which is hard to achieve in MCUs [Microcontroller units]. “FPGAs are semiconductor devices which contain programmable logic blocks and interconnection circuit”. The main challenges while hardware implementation of BSS algorithms is required high processing speed [Because of complex computations], Memory requirement, and power consumption. These challenges can easily solve by using FPGA. Optimization of a blind source separation algorithm can be done by using the technique called pipelining, Through this, the performance and accuracy of blind source signal separation are improved.