Publication

Abstract : Sign Least Mean Square (SLMS) adaptive filter can adapt dynamically based on corresponding filter output. One of the major applications of adaptive filter is Noise cancellation. In real time applications like medical computing, speed of the process developing hardware is essential hence the hardware realization of SLMS adaptive filter using Xilinx System generator is proposed in this work. The propose architecture aims to reduce convergence rate, path delay and increasing speed. In this work (i) Modified architecture is designed for a 8-tap SLMS adaptive filter and (ii) multiplier less structure for Modified DLMS Filter. The designed architecture tested for ECG signal. The functionality of the algorithm is verified in MATLAB with various ECG data from the MIT-BIH database as input. Both LMS and SLMS are designed, simulated, synthesized and implemented in Virtex-5 FPGA using Xilnix ISE 14.3 . The result shows 5% decrease in total real time router completion and also decrease in the number of adders and subtractors, the maximum combinational path delay has been reduced by 48.84% in Systolic Sign LMS Filter when compared to LMS Filter. Keywords— Adaptive filter, Least mean square(LMS), Sign Least mean square(SLMS) algorithm, systolic architecture.