Publication Type : Journal Article
Publisher : Journal of Electronic Design Technology
Source : Journal of Electronic Design Technology, Volume 5, Issue 1, p.1–15 (2014)
Campus : Amritapuri
School : Department of Computer Science and Engineering, School of Engineering
Department : Computer Science
Year : 2014
Abstract : In this paper, various types of device and interconnect scaling used for VLSI transistors are mentioned. Advanced device scaling techniques using SOI & FINFET technology are discussed for nano-devices. New technologies adopted at research level are stated here in brief.
Cite this Research Publication : Dr. Pritam Bhattacharjee and Arindam Sadhu, “VLSI Transistor and Interconnect Scaling Overview”, Journal of Electronic Design Technology, vol. 5, no. 1, pp. 1–15, 2014.