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Publication Type : Journal Article
Publisher : 2017 14th IEEE India Council International Conference (INDICON)
Source : 2017 14th IEEE India Council International Conference (INDICON) (2017)
Url : https://ieeexplore.ieee.org/document/8487762
Keywords : Computational modeling,Integrated circuit modeling,Adders,Computer architecture,Error compensation,Multiplexing,Semiconductor device modeling,Array based approximate arithmetic computing,multiplier,squarer,compressor
Campus : Coimbatore
School : School of Engineering
Center : Electronics Communication and Instrumentation Forum (ECIF)
Department : Electronics and Communication
Year : 2017
Abstract : Exact circuits produce accurate results but consume more power and area. Approximation is done to reduce the high consumption of area and power at the cost of accuracy. An array-based approximate arithmetic computing model (AAAC) is used for the reduction of error occurring in approximate binary arithmetic circuits. Although the model provides a trade-off between power, area and accuracy, these parameters can be improved further. The proposed model in this paper uses reduced number of truncated bits and a different compressor architecture for this improvement. An approximate 16 ×16 booth multiplier and an approximate 16 bit squarer are used as the applications. The proposed model for squarers reduce the power and area by 8.4% and 21.5% respectively and has an accuracy improvement of 3.4% when compared to the existing model. Similarly the proposed model for booth multiplier reduces the power and area by 4.5% and 3% respectively and has an accuracy improvement of 3.2% when compared with the existing one.
Cite this Research Publication : H. Haritha and Ramesh S. R., “Design of an Enhanced Array Based Approximate Arithmetic Computing Model for Multipliers and Squarers”, 2017 14th IEEE India Council International Conference (INDICON). 2017.