Publication Type : Patents
Source : Kolkata, India (2017)
Url : https://www.quickcompany.in/patents/voltage-keeper-based-robust-flip-flop-for-low-power-applications
Campus : Amritapuri
School : School of Engineering
Department : Computer Science
Year : 2017
Abstract : A D-flip-flop includes a master latch that receives a data input signal and generates a delayed inverted data input signal at a negative-level of a CLOCK signal, and a slave latch that receives the delayed inverted data input signal from the master latch circuit, and generates a further delayed data input signal at a positive level of the CLOCK signal.
Cite this Research Publication : Alak Majumder, Dr. Pritam Bhattacharjee, and Bipasha Nath, “Voltage Keeper Based Robust Flip Flop For Low Power Applications, Indian Patent File Application No. (Kolkata, India): 201731044358”, 2017.