Publication Type : Conference Paper
Publisher : Proceedings - 2009 2nd IEEE International Conference on Computer Science and Information Technology
Source : Proceedings - 2009 2nd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2009, Beijing, p.529-533 (2009)
ISBN : 9781424445196
Keywords : BHT, BTB, Clocks, Computer science, Dual edge triggered clock, Electric power utilization, ILP, Information technology, LDPR, Pipelines, power, RISC pipeline datapath
Campus : Amritapuri
School : School of Engineering
Department : Electronics and Communication
Year : 2009
Abstract :
Power consumption and performance are the crucial factors that determine the reliability of a CPU. In this paper, we discuss about some techniques that can be used for Instruction Level Parallelism which enhances the performance of the CPU by reducing the CPI there by reducing power consumption. We have also discussed about the power saving scheme using proper clocking strategies. We have mainly focused on implementing the simplified RISC pipeline datapath in HDL using two different clocking schemes to reduce the power consumption. We have adopted a new method which uses dual edge triggered clock that can decrease the power consumption of a pipelined datapath considerably, without sacrificing the throughput of the CPU. Finally, we have given the experimental result for our implementation of simplified RISC datapath. © 2009 IEEE.
Cite this Research Publication :
Rajesh Kannan Megalingam, T. Hassan, S., Vivek, P., Mohan, A., and M. Rao, T., “Power Consumption Reduction in CPU Datapath using a Novel Clocking Scheme”, in Proceedings - 2009 2nd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2009, Beijing, 2009, pp. 529-533